pow_test.log

pli_handbook_examples_pc verilog hdl 与C的接口的典型例子

Host command: verilog.exe
Command arguments:
    +cuzco_gui
    pow_test.v
    +gui

Verilog_XL_Turbo_NT 2.6.9 log file created Nov 24, 1998  21:52:47
Verilog_XL_Turbo_NT 2.6.9   Nov 24, 1998  21:52:47

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Compiling source file "pow_test.v"
Highest level modules:
test


$pow PLI application is being used.

$pow(2,3) returns          8
$pow(a,b) returns          1 (a=1 b=0)
L35 "pow_test.v": $stop at simulation time 4
Type ? for help
C1 > .

L36 "pow_test.v": $finish at simulation time 4
0 simulation events (use +profile or +listcounts option to count) + 2 accelerated events
CPU time: 3.3 secs to compile + 0.0 secs to link + 964.4 secs in simulation
End of Verilog_XL_Turbo_NT 2.6.9   Nov 24, 1998  22:08:52