代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5584772
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity decode1_int is
port(
o : out vl_logic;
i : in vl_logic
);
end decode1_int;
www.eeworm.com/read/159314/5584779
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s9 is
generic(
cds_action : string := "ignore";
init : integer := 0;
srval : integer :=
www.eeworm.com/read/159314/5584801
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s18 is
generic(
cds_action : string := "ignore";
init : integer := 0;
srval : integer :=
www.eeworm.com/read/159314/5584817
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnsn is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5584943
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity lut2_d is
generic(
init : integer := 0
);
port(
lo : out vl_logic;
o : ou
www.eeworm.com/read/159314/5584950
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnd_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi
www.eeworm.com/read/159314/5584966
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mult18x18 is
port(
p : out vl_logic_vector(35 downto 0);
a : in vl_logic_vector(17 downto 0);
www.eeworm.com/read/159314/5585050
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity timegrp is
generic(
cds_action : string := "ignore"
);
end timegrp;
www.eeworm.com/read/159314/5585051
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufns_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi
www.eeworm.com/read/159314/5585099
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity lut1_l is
generic(
init : integer := 0
);
port(
lo : out vl_logic;
i0 : in