_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity mult18x18 is
    port(
        p               : out    vl_logic_vector(35 downto 0);
        a               : in     vl_logic_vector(17 downto 0);
        b               : in     vl_logic_vector(17 downto 0)
    );
end mult18x18;