代码搜索:verilog hdl 是什么?
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www.eeworm.com/read/231894/14216690
html fft_example.html
A.h:hover { color: "#FF0000"; }
A.menu:link { text-decoration: none}
A.menu:visited{ text-decoration: none}
A.menu:hover {color: #EE9B06;}
A.submenu:link { text-decoration: none;}
www.eeworm.com/read/231687/14223291
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity KeypadScan_tb_v_tf is
end KeypadScan_tb_v_tf;
www.eeworm.com/read/231687/14223378
versim_par keypadscan.versim_par
KeypadScan.versim_par -- generated only for ProjNav status tracking
Simulation Model Target: Generic_Verilog
www.eeworm.com/read/231687/14223383
gfl projnav.gfl
# XST (Creating Lso File) :
KeypadScan.lso
# xst flow : RunXST
KeypadScan.syr
KeypadScan.prj
KeypadScan.sprj
KeypadScan.ana
KeypadScan.stx
KeypadScan.cmd_log
KeypadScan.ngc
KeypadScan.ngr
www.eeworm.com/read/231687/14223415
npl projnav.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT ProjNav
DESIGN projnav
DEVFAM xbr
DEVFAMTIME 0
DEVICE xc2c32a
DEVICETIME 1109962640
DEVPKG CP56
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
www.eeworm.com/read/127506/14351279
versim_xlate fen.versim_xlate
fen.versim_xlate -- generated only for ProjNav status tracking
Simulation Model Target: Generic_Verilog
www.eeworm.com/read/127506/14351421
versim_map fen.versim_map
fen.versim_map -- generated only for ProjNav status tracking
Simulation Model Target: Generic_Verilog
www.eeworm.com/read/127506/14351426
versim_par fen.versim_par
fen.versim_par -- generated only for ProjNav status tracking
Simulation Model Target: Generic_Verilog
www.eeworm.com/read/228929/14357593
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity top_tb is
generic(
periode : integer := 25
);
end top_tb;
www.eeworm.com/read/221711/14726499
qmsg cmp.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: