projnav.npl

来自「适用于FPGA的SOPC方面的元器件添加」· NPL 代码 · 共 39 行

JDF G
// Created by Project Navigator ver 1.0
PROJECT ProjNav
DESIGN projnav
DEVFAM xbr
DEVFAMTIME 0
DEVICE xc2c32a
DEVICETIME 1109962640
DEVPKG CP56
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
DOCUMENT post_fit_sim.do
DOCUMENT behavioral_sim.do
STIMULUS tb.v
SOURCE KeypadScan.v
DEPASSOC KeypadScan KeypadScan.ucf
[Normal]
p_SimUseCustom_behav=xstvlg, xbr, Test Fixture.t_MSimulateBehavioralVerilogModel, 1109963364, True
p_SimUseCustom_postPar=xstvlg, xbr, Test Fixture.t_MSimulatePostPlace&RouteVerilogModel, 1109963374, True
xcpldFitDesTriMode=xstvlg, xbr, Verilog.t_vm6File, 1109963192, Pullup
xcpldFitDesUnused=xstvlg, xbr, Verilog.t_vm6File, 1109963192, Pullup
_VerilogSimDo_behav=xstvlg, xbr, Test Fixture.t_MSimulateBehavioralVerilogModel, 1109963364, False
_VerilogSimDo_post=xstvlg, xbr, Test Fixture.t_MSimulatePostPlace&RouteVerilogModel, 1109963374, False
_VerilSimCustom_behav=xstvlg, xbr, Test Fixture.t_MSimulateBehavioralVerilogModel, 1109963364, C:\mikeg\Designs\Dan_Cox\KeypadScan_ProjNav_3_4_05\ProjNav\behavioral_sim.do
_VerilSimCustom_postPar=xstvlg, xbr, Test Fixture.t_MSimulatePostPlace&RouteVerilogModel, 1109963374, C:\mikeg\Designs\Dan_Cox\KeypadScan_ProjNav_3_4_05\ProjNav\post_fit_sim.do
[STATUS-ALL]
KeypadScan.ngcFile=WARNINGS,1109962597
[STRATEGY-LIST]
Normal=True