代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/344458/7100009
npl uart_send.npl
JDF E
// Created by ISE ver 1.0
PROJECT uart_send
DESIGN uart_send Normal
DEVKIT XC95108 PC84
DEVFAM xc9500
FLOW XST Verilog
MODULE send.v
MODSTYLE send Normal
[STRATEGY-LIST]
Normal=True,
www.eeworm.com/read/344458/7100010
npl send.npl
JDF E
// Created by ISE ver 1.0
PROJECT send
DESIGN send Normal
DEVKIT XC95108 PC84
DEVFAM xc9500
FLOW XST Verilog
MODULE send.v
MODSTYLE uart_send Normal
[STRATEGY-LIST]
Normal=True, 1038
www.eeworm.com/read/344458/7100029
_prj send._prj
insert `timescale 1ns/1ns
include
include send.v
include d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
www.eeworm.com/read/344458/7100067
_prj receive._prj
insert `timescale 1ns/1ns
include
include receive.v
include d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
www.eeworm.com/read/344458/7100080
npl receive.npl
JDF E
// Created by ISE ver 1.0
PROJECT receive
DESIGN receive Normal
DEVKIT XC95108 PC84
DEVFAM xc9500
FLOW XST Verilog
MODULE receive.v
MODSTYLE uart_rec Normal
[STRATEGY-LIST]
Normal=Tr
www.eeworm.com/read/264839/7110822
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity add_12b_tp is
end add_12b_tp;
www.eeworm.com/read/264839/7110877
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity add_20b_tp is
end add_20b_tp;
www.eeworm.com/read/421150/7118844
v vdefs.v
// These are the verilog defines that match the systemc defines vdefs.h
`define IDLE 0
`define START 1
`define STEP1 2
`define STEP2 3
`define STEP3 4
`define STEP4 5
`define DONE 6
www.eeworm.com/read/202633/7124942
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_testbench is
generic(
tp : integer := 1;
brp : integer := 4
);
end can_testbench;
www.eeworm.com/read/411873/7151081
hif clkdiv.hif
Version 7.0 Build 33 02/05/2007 SJ Full Version
36
1980
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
--