代码搜索：verilog hdl 是什么？

找到约 10,000 项符合「verilog hdl 是什么？」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/421122/10754387

hif led2.hif

Version 7.0 Build 33 02/05/2007 SJ Full Version 36 1980 OFF OFF OFF OFF OFF FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Start Library Paths -- --
·
www.eeworm.com/read/349305/10836686

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity SRAM_16Bit_512K_tb is end SRAM_16Bit_512K_tb;
·
www.eeworm.com/read/349305/10836933

qmsg sramtest.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I
·
www.eeworm.com/read/273951/10893288

qmsg fdiv.tan.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
·
www.eeworm.com/read/273951/10893387

qmsg dispselect.tan.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
·
www.eeworm.com/read/273951/10893455

rpt main.map.rpt

Analysis & Synthesis report for main Mon Jul 17 23:30:02 2006 Version 4.2 Build 157 12/07/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal No
·
www.eeworm.com/read/273951/10893521

qmsg main.tan.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
·
www.eeworm.com/read/273951/10893938

qmsg dispdecoder.tan.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
·
www.eeworm.com/read/273442/10915998

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity uart_51_tb is generic( clk_period : integer := 6 ); end uart_51_tb;
·
www.eeworm.com/read/270382/11039830

rpt colorbar.map.rpt

Analysis & Synthesis report for ColorBar Mon Jun 27 23:34:29 2005 Version 5.0 Build 148 04/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Lega
·