代码搜索:verilog hdl 是什么?

找到约 10,000 项符合「verilog hdl 是什么?」的源代码

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c qmc__hdl.c

/************************************************************************/ /* */ /*
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v hdl_demo.v

module hdl_demo(rst, clk, start_value, in_a, in_b, in_c, accum_a, accum_b, result); input rst, clk, in_a, in_b, in_c; input [7:0] accum_a, accum_b; input [31:0] start_value; output [7:0] result;
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vhd hdl_demo.vhd

library IEEE; use IEEE.std_logic_1164.all; --lab2 --lab2 entity hdl_demo is port (rst, clk,in_a,in_b,in_c : in std_logic; accum_a, accum_b : in std_logic_vector(7 downto 0);
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plg hdl_demo.plg

@P: Part : EP1S10FC780-5 @P: Worst Slack : -5.041 @P: clk - Estimated Frequency : NA @P: clk - Requested Frequency : 150.0 MHz @P: clk - Estimated Period : NA @P: clk - Requested Period : 6
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txt hdl.var.txt

#***************************************************************************** # NCSIM hdl.var template * #***************************************
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v hdl_demo.v

module hdl_demo(rst, clk, start_value, in_a, in_b, in_c, accum_a, accum_b, result); input rst, clk, in_a, in_b, in_c; input [7:0] accum_a, accum_b; input [31:0] start_value; output [7:0] result;
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vhd hdl_demo.vhd

library IEEE; use IEEE.std_logic_1164.all; --lab2 --lab2 entity hdl_demo is port (rst, clk,in_a,in_b,in_c : in std_logic; accum_a, accum_b : in std_logic_vector(7 downto 0);
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v hdl_demo.v

module hdl_demo(rst, clk, start_value, in_a, in_b, in_c, accum_a, accum_b, result); input rst, clk, in_a, in_b, in_c; input [7:0] accum_a, accum_b; input [31:0] start_value; output [7:0] result;
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vhd hdl_demo.vhd

library IEEE; use IEEE.std_logic_1164.all; --lab2 --lab2 entity hdl_demo is port (rst, clk,in_a,in_b,in_c : in std_logic; accum_a, accum_b : in std_logic_vector(7 downto 0);
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edf hdl_demo.edf

(edif hdl_demo (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2004 6 16 16 5 5) (author "Synplicity, Inc.") (program