代码搜索：verilog hdl 开发教程

找到约 10,000 项符合「verilog hdl 开发教程」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/160187/5576478

repository

usb_funct/rtl/verilog
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www.eeworm.com/read/154095/5642320

prj prescale_counter.prj

verilog work prescale_counter.v
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www.eeworm.com/read/295493/8158256

repository

usb_funct/rtl/verilog
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www.eeworm.com/read/172338/9713093

prj can_fifo.prj

verilog work can_fifo.v
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www.eeworm.com/read/235010/14089098

prj ddr_command.prj

verilog work ddr_command.v
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www.eeworm.com/read/478173/6720921

v v_hier_noport.v

// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2009 by Wilson Snyder. module v_hier_nopor
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www.eeworm.com/read/478173/6720927

v v_hier_subsub.v

// DESCRIPTION: Verilog-Perl: Example Verilog for testing package // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2009 by Wilson Snyder. module v_hier_subsu
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www.eeworm.com/read/478173/6720966

t 35_sigparser.t

#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2009 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify
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www.eeworm.com/read/478173/6720974

out 80_vppreproc_none.out

`line 1 "verilog/inc2.v" 1 // DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2000-2009 by Wilson Snyder. At fi
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www.eeworm.com/read/248071/12603685

makefile

OBJS=../classes/List.o \ ../classes/IODecl.o \ ../classes/Util.o \ ../classes/Module.o \ ../classes/BitVec.o OPTS=-lfl -olexp YACC=bison CC=g++ all: parser parser: verilog-y verilog-lex ${YACC} -
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