makefile

將Verilog設計轉成VHDL設計的程式

OBJS=../classes/List.o \
../classes/IODecl.o \
../classes/Util.o \
../classes/Module.o \
../classes/BitVec.o

OPTS=-lfl -olexp

YACC=bison
CC=g++

all: parser

parser: verilog-y verilog-lex
	${YACC} -d verilog-y
	flex verilog-lex
	${CC} -c lex.yy.c
	${CC} -c verilog-y.tab.c
	${CC} lex.yy.o verilog-y.tab.o $(OBJS) main.c $(OPTS)


clean:
	rm -f *~
	rm -f core
	rm -f *.o

tar: *
	tar cvfz tar/v2vhdl.tgz *