代码搜索：verilo

找到约 17 项符合「verilo」的源代码

代码结果 17
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/155522/11866907

transcript

# Reading E:/Program Files/Modelsim/win32/../tcl/vsim/pref.tcl # // ModelSim SE 6.0 Aug 19 2004 # // # // Copyright Mentor Graphics Corporation 2004 # // All Rights Reserved. # /
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www.eeworm.com/read/446938/1708203

makefile

########################################################################## # # DUT Sources # ########################################################################## DUT_SRC_DIR=../../../rtl/verilo
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www.eeworm.com/read/446938/1708204

old makefile.old

########################################################################## # # DUT Sources # ########################################################################## DUT_SRC_DIR=../../../rtl/verilo
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www.eeworm.com/read/446938/1708206

makefile~

########################################################################## # # DUT Sources # ########################################################################## DUT_SRC_DIR=../../../rtl/verilo
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www.eeworm.com/read/308751/13693503

ndo arm.ndo

## NOTE: Do not edit this file. ## Auto generated by Project Navigator for Verilog Post-Translate Simulation ## vlib work ## Compile Post-Translate Model for Module armtst vlog "C:/Xilinx/verilo
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www.eeworm.com/read/190958/5169906

xco program.xco

# BEGIN Project Options SET flowvendor = Foundation_iSE SET vhdlsim = True SET verilogsim = True SET workingdirectory = C:\XUP\Markets\PLDs\Workshops\courses\v82_fpga_flow\xupv2pro\labsolutions\verilo
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www.eeworm.com/read/190958/5170065

xco program.xco

# BEGIN Project Options SET flowvendor = Foundation_iSE SET vhdlsim = True SET verilogsim = True SET workingdirectory = C:\XUP\Markets\PLDs\Workshops\courses\v82_fpga_flow\xupv2pro\labsolutions\verilo
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www.eeworm.com/read/263610/4301531

makefile

SHELL = /bin/sh #.QUIET # test_bench/test_bench_top.v MC_TARGETS= ../../../rtl/verilog/mc_top.v \ ../../../rtl/verilog/mc_wb_if.v \ ../../../rtl/verilog/mc_cs_rf.v \ ../../../rtl/verilo
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www.eeworm.com/read/308966/13685133

dls lib.dls

DLSL 1 CmdCtrl.VerilogView U0586814.DLS KBSCAN.VHDLVIEW U3764425.DLS KBSCAN-BEHAVE.SYNTHESISVIEW U2993218.DLS KBSCAN-BEHAVE.VHDLVIEW U9514177.DLS ModSel.VerilogView U4836290.DLS mainctrl.Verilo
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www.eeworm.com/read/308962/13685871

dls lib.dls

DLSL 1 CmdCtrl.VerilogView U0586814.DLS KBSCAN.VHDLVIEW U3764425.DLS KBSCAN-BEHAVE.SYNTHESISVIEW U2993218.DLS KBSCAN-BEHAVE.VHDLVIEW U9514177.DLS ModSel.VerilogView U4836290.DLS mainctrl.Verilo
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