代码搜索：vHD
找到约 10,000 项符合「vHD」的源代码
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www.eeworm.com/read/353021/10477831
vhd vhd.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY main IS
PORT(
IN_CPLDCS, IN_RD: IN STD_LOGIC;
IN_SIGNAL: IN STD_LOGIC_V
www.eeworm.com/read/246102/12756417
vhd .vhd
--megafunction wizard: %Altera SOPC Builder%
--GENERATION: STANDARD
--VERSION: WM1.0
www.eeworm.com/read/430385/8751948
vhd medfilter_vhd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in
www.eeworm.com/read/418552/10940272
vhd vhd_top.vhd
library ieee;
use ieee.std_logic_1164.all;
entity Gold_Code is
generic (width : integer := 1);
port ( Clk :in std_logic;
Enable : in std_logic;
Fill_En_A : in std_logic;
Fill_En_B : in std_logic
www.eeworm.com/read/418552/10940275
vhd vhd_subb.vhd
library ieee;
use ieee.std_logic_1164.all;
entity LFSR_B is
generic (cycleB0 : integer := 26;
cycleB20 : integer := 21;
width :integer := 1);
port ( Clk :in std_logic;
Enable :
www.eeworm.com/read/418552/10940277
vhd vhd_suba.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity LFSR_A is
generic (cycleA0 : integer := 26;
cycleA3 : integer := 4;
width :integer := 1);
port ( Clk :in std_logic;
Enable : i