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低电平脉冲状态的捕抓（多个）缓存并 用减小的并口线输出

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;


ENTITY main IS
	PORT(
		IN_CPLDCS, IN_RD: IN	STD_LOGIC;
		IN_SIGNAL: IN	STD_LOGIC_VECTOR(15 downto 0);
		IN_GCLK:	IN	STD_LOGIC;
		OUT_DATA	: OUT	STD_LOGIC_VECTOR(7 downto 0);

		IN_ANACTL:	IN	STD_LOGIC_VECTOR(1 downto 0);
		OUT_ANACTL:	OUT	STD_LOGIC_VECTOR(7 downto 0)
		);

END main ;


ARCHITECTURE behav OF main IS
	--TYPE STATE IS (WAITTING,TSTSIGNAL,DATAOUT1,DATAOUT2,DATAOUT3,DATAOUT4);
	TYPE STATE IS (WAITTING,TSTSIGNAL,DATAOUT);
	SIGNAL CURR_STATE:	STATE;
	SIGNAL REG_DATA: STD_LOGIC_VECTOR(15 downto 0);	
	SIGNAL RD_REG: STD_LOGIC;	

BEGIN
	--analog switch control expanded
--	OUT_ANACTL(7 downto 6)<=IN_ANACTL;
--	OUT_ANACTL(5 downto 4)<=IN_ANACTL;
--	OUT_ANACTL(3 downto 2)<=IN_ANACTL;
--	OUT_ANACTL(1 downto 0)<=IN_ANACTL;

	--  Process Statement
	testsignal:
	PROCESS (IN_GCLK)
		VARIABLE cnt4rd: integer range 0 to 5;
		--VARIABLE rdflag_c,rdflag_p: bit;
		VARIABLE rd_start: bit;
		--VARIABLE REG_DATA: BIT_VECTOR(31 downto 0);	

	BEGIN

		IF RISING_EDGE(IN_GCLK) THEN

			CASE CURR_STATE IS
				WHEN WAITTING=>
					--REG_DATA<="00000000000000000000000000000000";
					IF IN_CPLDCS='0' THEN					
						CURR_STATE<=TSTSIGNAL;
					END IF;
				   				    
				WHEN TSTSIGNAL=>
					--FOR i IN IN_SIGNAL'HIGH DOWNTO IN_SIGNAL'LOW+1 LOOP
					FOR i IN 15 DOWNTO 0 LOOP
						IF(IN_SIGNAL(i)='0') THEN
							REG_DATA(i)<='1';
							--REG_DATA(i):='1';
						END IF;
					END LOOP;
					IF IN_CPLDCS='1' THEN
						CURR_STATE<=DATAOUT;
					END IF;

				WHEN DATAOUT=>
				
					IF IN_CPLDCS='0' THEN	--if cnt4rd always <4,and IN_CPLDCS change to 0,goto TST state				
						REG_DATA<="0000000000000000";
						CURR_STATE<=TSTSIGNAL;
					END IF;
					
					IF (cnt4rd=2) THEN
						REG_DATA<="0000000000000000";
						cnt4rd:=0;
						CURR_STATE<=WAITTING;
					END IF;

					RD_REG<=IN_RD;--2úéú?àáú×′ì?
					IF(RD_REG='0' and IN_RD='1') THEN--upì??D??
						rd_start:='1';
					ELSIF(RD_REG='1' and IN_RD='0' AND rd_start='1') THEN --down
						cnt4rd:=cnt4rd+1;
						rd_start:='0';
					END IF;
						
--					IF(IN_RD='1') THEN
--						rd_start:='1';
--
--					ELSIF(IN_RD='0' AND rd_start='1') THEN
--						cnt4rd:=cnt4rd+1;
--						rd_start:='0';
--					END IF;

					IF(rd_start='1')THEN
						--case cnt4rd is
							--when 0 =>
						IF(cnt4rd=0)THEN
							OUT_DATA(7)<=REG_DATA(15);
							OUT_DATA(6)<=REG_DATA(14);
							OUT_DATA(5)<=REG_DATA(13);
							OUT_DATA(4)<=REG_DATA(12);
							OUT_DATA(3)<=REG_DATA(11);
							OUT_DATA(2)<=REG_DATA(10);
							OUT_DATA(1)<=REG_DATA(9);
							OUT_DATA(0)<=REG_DATA(8);
--							FOR k IN 7 DOWNTO 0 LOOP
--								OUT_DATA(k)<=REG_DATA(k+24);
--							end loop;
							--when 1 =>
						ELSIF(cnt4rd=1)THEN
							OUT_DATA(7)<=REG_DATA(7);
							OUT_DATA(6)<=REG_DATA(6);
							OUT_DATA(5)<=REG_DATA(5);
							OUT_DATA(4)<=REG_DATA(4);
							OUT_DATA(3)<=REG_DATA(3);
							OUT_DATA(2)<=REG_DATA(2);
							OUT_DATA(1)<=REG_DATA(1);
							OUT_DATA(0)<=REG_DATA(0);
						
--							when others =>
--								null;
--							end case;
						END IF;

					END IF;	



				WHEN OTHERS =>
				    NULL;
			END CASE;
		END IF;
			

	END PROCESS testsignal;


	
	
END behav;