代码搜索：trigger
找到约 3,730 项符合「trigger」的源代码
代码结果 3,730
www.eeworm.com/read/124581/14558268
c fet140_adc12_10.c
//******************************************************************************
// MSP-FET430P140 Demo - ADC12, Trigger Conversion With Timer_A
//
// Description: Trigger an A/D conversion with
www.eeworm.com/read/223174/14650597
c fet140_adc12_10.c
//******************************************************************************
// MSP-FET430P140 Demo - ADC12, Trigger Conversion With Timer_A
//
// Description: Trigger an A/D conversion with
www.eeworm.com/read/17055/709456
js jquerysamplescript.js
$(function () {
$('#jticker').ticker({
cursorList: ' ',
rate: 40,
delay: 4000
}).trigger('play');
$('.next').live('click', function(){
$('#jticker').trigger({
type: 'play'
}
www.eeworm.com/read/286972/8734108
h extint.h
#ifndef EXTINT_H
#define EXTINT_H
#include "global.h"
#define EXTINT0 0x00 ///< External Interrupt 0
#define EXTINT1 0x01 ///< External Interrupt 1
#define EXTINT2 0x02 ///< Exter
www.eeworm.com/read/183260/9173780
sql firingorder.sql
REM firingOrder.sql
REM Chapter 11, Oracle9i PL/SQL Programming by Scott Urman
REM This script demonstrates the order of trigger firing.
DROP SEQUENCE trig_seq;
CREATE SEQUENCE trig_seq
STA
www.eeworm.com/read/178467/9395505
txt 触发器.txt
/*
功能说明：附件全部删除后，“附件名”为空，同时将“附件号”设为“0”
触发器类型：AFTER UPDATE
涉及数据对象：XT_TD_USERMESSAGE
制作人：刘晓颖
制做日期：2003-1-8
*/
CREATE TRIGGER tr_XT_TD_USERMESSAGE_U ON dbo.XT_TD_USERMESSAGE
AFTER UPDATE
AS
IF
www.eeworm.com/read/357120/10215905
h global.h
#include "Core_Global.h"
#include "Barrier.h"
#include "CharICS.h"
#include "Chars.h"
#include "Frustum.h"
#include "MCL.h"
#include "MSL.h"
#include "Script.h"
#include "Spell.h"
#include
www.eeworm.com/read/267307/6933119
vhd edge.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity EDGE is
port (
ADDATA: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
VOLTAGE_TRI : IN std_logic_vector (7 downto 0);
TRIGGER : OUT STD_LOGIC
)
www.eeworm.com/read/267307/6933141
vhd conv_single.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity CONV_SINGLE is
port (
CLK : IN STD_LOGIC;
SINGLE : in std_logic;
-- LOCKS : IN STD_LOGIC;
ADDATA: IN STD_LOGIC_VECTOR (7 DOWNTO
www.eeworm.com/read/267307/6933418
vhd edge.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity EDGE is
port (
ADDATA: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
VOLTAGE_TRI : IN std_logic_vector (7 downto 0);
TRIGGER : OUT STD_LOGIC
)