代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
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v uart_testbench_defines.v
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_testbench_defines.v
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v testbench_wd_reg.v
// testbench for write data register
`include "wd_reg.v"
module top;
reg sysclk;
reg [31:0] WD_Bus_Write;
reg WD_DBE, WD_Load;
wire [31:0] WD_DOUT;
integer file; //the number
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v testbench_regfile2.v
/////////////////////////////////////////////////////////////////
// Verilog Test Bench v2.0, 3-29-2000 //
// ECE 371 EMR, Spring 2000 //
//
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v testbench_regfile4.v
/////////////////////////////////////////////////////////////////
// Verilog Test Bench v2.0, 4-3-2000 //
// ECE 371 EMR, Spring 2000 //
//
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v testbench_arm7.v
/////////////////////////////////////////////////////////////////
// ARM7 TOP LEVEL TEST BENCH v1.0, 4-6-2000 //
// ECE 371 EMR, Spring 2000 //
//
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v testbench_addr_reg.v
`include "addr_reg.v"
module top;
reg [31:0] AR_Bus_Alu, AR_Bus_PC, AR_Bus_PC_4;
reg [1:0] AR_Bus_Sel;
reg sysclk;
wire [31:0] AR_Output_Bus;
integer file; //the number for the
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v testbench_regfile3.v
/////////////////////////////////////////////////////////////////
// Verilog Test Bench v2.0, 3-29-2000 //
// ECE 371 EMR, Spring 2000 //
//
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v hw3testbench.v
`define period 100
`define quarter_period 25
`timescale 100ms/1ms //declare the time unit and its precision
`define clk_count 1 //define the clock delay is 1 time unit,i.e. 10ms
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vhd 41_generic_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity test_decoder3 is
end test_decoder3;
architecture BENCH of test_decoder3 is
component decoder3
port(
Sel : Bit_vector ( 1 to 3 );
Do
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vhd 53_counter_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity testcnt is
end testcnt;
use work.mycntpkg.all;
architecture mytest of testcnt is
signal clk,rst:std_logic;
signal cnt:std_logic_vector(2 d