代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/109660/6173092
do compile_and_run_rtl_fullmodel_v.do
vlog "$env(QUARTUS_ROOTDIR)/eda/sim_lib/excalibur/stripe_model_nt/ModelGen/models/epxa10/r0/mti_modelsim_verilog/alt_exc_stripe.v"
vlog ../../embedded_stripe.v
vlog ../../../testbench/ahb_bus_tb
www.eeworm.com/read/109660/6173105
do compile_and_run_rtl_fullmodel_v.do
vlog "$env(QUARTUS_ROOTDIR)/eda/sim_lib/excalibur/stripe_model_nt/ModelGen/models/epxa10/r0/mti_modelsim_verilog/alt_exc_stripe.v"
vlog ../../embedded_stripe.v
vlog ../../../testbench/ahb_bus_tb
www.eeworm.com/read/18102/774812
v disasm_debug.v
`include "timescale.v"
module testbench();
reg rst;
reg clk;
reg [3:0] ins_len;
reg [31:0] opcode, opcode2;
reg [7:0] mem [0:16'h1FFF];
reg [7:0] ip_next;
always #20 clk = ~clk
www.eeworm.com/read/18102/774820
vcd dump.vcd
$date
Mon Jul 24 20:52:49 2006
$end
$version
Icarus Verilog
$end
$timescale
10ps
$end
$scope module testbench $end
$var reg 1 ! clk $end
$var reg 4 " ins_len[3:0] $end
$var reg 8 # ip_n
www.eeworm.com/read/423217/10579069
bak test2.v.bak
//test in two different clk with transmitter2 and receiver2
module testbench2();
reg Clk1,Clk2,Reset;
wire BitWire;
reg [3:0] ClkCounter1;
reg [3:0] ClkCounter2;
reg in_DataEnable;
reg [7:0] in_D
www.eeworm.com/read/423217/10579081
v test2.v
//test in two different clk with transmitter2 and receiver2
module testbench2();
reg Clk1,Clk2,Reset;
wire BitWire;
reg [3:0] ClkCounter1;
reg [3:0] ClkCounter2;
reg in_DataEnable;
reg [7:0] in_D
www.eeworm.com/read/109660/6173102
do compile_and_run_timing_busfuncmodel_v.do
vlog "$env(QUARTUS_ROOTDIR)/eda/sim_lib/excalibur/lpm/alt_exc_stripe_bfm.v"
vlog "$env(QUARTUS_ROOTDIR)/eda/sim_lib/apex20ke_atoms.v"
vlog ../../../testbench/ahb_bus_tb.v
vlog Multi_Master_Re
www.eeworm.com/read/109660/6173115
do compile_and_run_timing_busfuncmodel_v.do
vlog "$env(QUARTUS_ROOTDIR)/eda/sim_lib/excalibur/lpm/alt_exc_stripe_bfm.v"
vlog "$env(QUARTUS_ROOTDIR)/eda/sim_lib/apex20ke_atoms.v"
vlog ../../../testbench/ahb_bus_tb.v
vlog Multi_Master_Re
www.eeworm.com/read/204639/5032122
ref hdllib.ref
AR motorwave testbench_arch F:/practice/PLD/motor/motorwave.vhw sub00/vhpl03 1164011168
EN motor NULL F:/practice/PLD/motor/motor.vhd sub00/vhpl00 1164011132
AR motor action F:/practice/PLD/motor/mo
www.eeworm.com/read/167222/9975037
v test_pc.v
module testbench_pc;
wire clk,reset,load_enable,count_enable;
wire [7:0] pc_out,pc_in;
PC p (pc_out,pc_in,clk,reset,load_enable,count_enable);
test t (pc_out,pc_in,clk,reset,load_