代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/293898/3927713
tf jc2_test.tf
`timescale 1ns/1ns
// Timing simulation test fixture for jc2_top Verilog design.
module testbench;
reg clk;
reg stop;
reg left;
reg right;
wire [3:0] q;
reg PRLD;
jc2_top UUT (
.left(left),
www.eeworm.com/read/434118/1874871
_info
m255
13
cModel Technology
dC:\Peter\Subjects\HET515\Laboratory\Virtex-II_Board_Expansion\pcores\display_controller_v1_00_a\devl\projnav
Euser_logic_testbench_vhd
w1173419568
DP ieee numeric_std [B
www.eeworm.com/read/383754/2613760
tf jc2_test.tf
`timescale 1ns/1ns
// Timing simulation test fixture for jc2_top Verilog design.
module testbench;
reg clk;
reg stop;
reg left;
reg right;
wire [3:0] q;
reg PRLD;
jc2_top UUT (
.left(left),
www.eeworm.com/read/383754/2614009
tf jc2_test.tf
`timescale 1ns/1ns
// Timing simulation test fixture for jc2_top Verilog design.
module testbench;
reg clk;
reg stop;
reg left;
reg right;
wire [3:0] q;
reg PRLD;
jc2_top UUT (
.left(left),
www.eeworm.com/read/135419/13934277
elb mega.elb
(_unit VERILOG 1.152.1.136 (SAP_1_tb 0 9 (SAP_1_tb 0 9 ))
(_version v27)
(_time 1117625255825 2005.06.01 19:27:35)
(_source (\.\\src\\TestBench\\SAP_1_TB.v\))
(_use (std(standard))(vl(verilog_logi
www.eeworm.com/read/235764/14053480
v tb.v
`timescale 1ns/1ps
module testbench();
parameter DATA_SIZE = 8;
parameter FIFO_DEPTH = 16;
reg reset;
reg clk;
reg [DATA_SIZE-1:0] din;
reg web;
reg reb;
reg full;
reg empty;
reg [DATA_
www.eeworm.com/read/235435/14071980
m xk_cmpr.m
%function fft_cmpr;
ax_font_size = 22;
ax_lab_size = 24;
fmt = '-tiff -deps';
print_flag=0;
n = 16;
fname_c_model = input('C model input data: ','s');
fname_vhdl = input('testbench output d
www.eeworm.com/read/158843/10724388
wsp cordic_beh.wsp
[General]
CurrentVersion=103
[CACHEDOC|Aldec.Hde.HdePlugIn.7|g:\2006春季课程\通信系统仿真与SOC集成-周祖成-2005春\1_A_作业\HDesign\HDesign_lib\hdl\cordic_testbench_struct.vhd|]
CurrentLine=51
CurrentColumn=55
Bookma
www.eeworm.com/read/440140/7693462
vcd flash.vcd
$date
Tue Mar 09 16:30:58 2004
$end
$version
ModelSim Version 5.8b
$end
$timescale
1ps
$end
$scope module testbench $end
$scope module uut $end
$var wire 1 ! HALFCLK $end
$var wire 1 " P_Q7 $end
$v
www.eeworm.com/read/306496/13743574
v disasm_debug.v
`include "timescale.v"
module testbench();
reg rst;
reg clk;
reg [3:0] ins_len;
reg [31:0] opcode, opcode2;
reg [7:0] mem [0:16'h1FFF];
reg [7:0] ip_next;
always #20 clk = ~clk