代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/405362/2292828
cpp xsimtestbench_arch.cpp
#include "work/t_l_1_0/testbench_arch.h"
static const char * HSimCopyRightNotice = "Copyright 2004-2005, Xilinx Inc. All rights reserved.";
#include "C:/Xilinx/vhdl/hdp/ieee/std_logic_1164/std_logic
www.eeworm.com/read/405362/2292839
cpp xsimtestbench_arch.cpp
#include "work/t_eitht_0s/testbench_arch.h"
static const char * HSimCopyRightNotice = "Copyright 2004-2005, Xilinx Inc. All rights reserved.";
#include "C:/Xilinx/vhdl/hdp/ieee/std_logic_1164/std_lo
www.eeworm.com/read/405362/2292847
cpp xsimtestbench_arch.cpp
#include "work/t_eight_0s/testbench_arch.h"
static const char * HSimCopyRightNotice = "Copyright 2004-2005, Xilinx Inc. All rights reserved.";
#include "C:/Xilinx/vhdl/hdp/ieee/std_logic_1164/std_lo
www.eeworm.com/read/383505/8941209
v booth16_test.v
module testbench();
parameter WIDTH = 16;
reg CLK, RESET;
reg [WIDTH-1:0]A, B;
wire [WIDTH+WIDTH-1:0]P;
Booth16 m1(.CLK(CLK), .RESET(RESET), .A(A), .B(B), .P(P));
initial
CLK = 1'b0;
www.eeworm.com/read/170175/9815480
m xk_cmpr.m
%function fft_cmpr;
ax_font_size = 22;
ax_lab_size = 24;
fmt = '-tiff -deps';
print_flag=0;
n = 16;
fname_c_model = input('C model input data: ','s');
fname_vhdl = input('testbench output d
www.eeworm.com/read/168079/9940167
m xk_cmpr.m
%function fft_cmpr;
ax_font_size = 22;
ax_lab_size = 24;
fmt = '-tiff -deps';
print_flag=0;
n = 16;
fname_c_model = input('C model input data: ','s');
fname_vhdl = input('testbench output d
www.eeworm.com/read/424814/10410226
syn mico8uart_xo.syn
JDF B
// Created by Version 7.2
PROJECT mico8uart_xo
DESIGN mico8uart_xo Normal
DEVKIT LCMXO2280C-5T144C
ENTRY Pure Verilog HDL
TESTFIXTURE ..\..\testbench\uart_tb.v
MODULE ..\..\source\modem.
www.eeworm.com/read/423217/10578970
v test3.v
//test in two different clk with transmitter and receiver
module testbench3();
reg Clk1,Clk2,Reset;
wire BitWire;
reg [3:0] ClkCounter1;
reg [3:0] ClkCounter2;
reg in_DataEnable;
reg [7:0] in_Data
www.eeworm.com/read/423217/10579107
bak test3.v.bak
//test in two different clk with transmitter and receiver
module testbench3();
reg Clk1,Clk2,Reset;
wire BitWire;
reg [3:0] ClkCounter1;
reg [3:0] ClkCounter2;
reg in_DataEnable;
reg [7:0] in_Data
www.eeworm.com/read/462120/7209116
m xk_cmpr.m
%function fft_cmpr;
ax_font_size = 22;
ax_lab_size = 24;
fmt = '-tiff -deps';
print_flag=0;
n = 16;
fname_c_model = input('C model input data: ','s');
fname_vhdl = input('testbench output d