test3.v

简单的uart状态机的编写

//test in two different clk with transmitter and receiver
module testbench3();    
reg Clk1,Clk2,Reset;
wire BitWire;
reg [3:0] ClkCounter1;
reg [3:0] ClkCounter2;
reg in_DataEnable;
reg [7:0] in_Data;
wire [7:0] out_Data;

//connect transmitter and receiver
transmitter DUT1(.in_clk(Clk1),
                 .in_resetn(Reset),
                 .in_Data(in_Data),
                 .in_DataEnable(in_DataEnable),
                 .out_NextData(NextData),
                 .out_Bit(BitWire)
                 );
receiver DUT2(.in_clk(Clk2),
              .in_resetn(Reset),
              .in_bit(BitWire),
              .out_Data(out_Data),
              .out_DataEnable(out_DataEnable),
              .out_ParityError(out_ParityError),
              .out_FrameError(out_FrameErrror)
              );

initial
   begin
     $dumpfile("uart.vcd");
     $dumpvars;
     $dumpon;
     Clk1 = 1'b0;
     Clk2 = 1'b0;
     Reset = 1'b0;
     #100 Reset=1'b1;
   end


always #10          
   Clk1 <= !Clk1;
always #9.5         
   Clk2 <= !Clk2;
   
always @(posedge Clk1 or negedge Reset)
   if(!Reset)
      ClkCounter1 <= 0;
   else
      ClkCounter1 <= ClkCounter1 + 1;
      
always @(posedge Clk2 or negedge Reset)
   if(!Reset)
      ClkCounter2 <= 0;
   else
      ClkCounter2 <= ClkCounter2 + 1;


always @(posedge Clk1 or negedge Reset )
 if(!Reset)
      begin
      in_Data=8'b0;
      in_DataEnable =1'b0;
      end
   else
   begin
   if((NextData) & (ClkCounter1 == 0))
     begin
     in_Data=$random;
     in_DataEnable =1'b1;
     $display("Issue data %h", in_Data);
     end
   else
     begin
     //in_Data=8'b0;
     in_DataEnable =1'b0;
     end
   end
   
   
always @(posedge out_DataEnable)
if(out_DataEnable) 
  begin
     if(out_ParityError)
        $display("Parity Error");
     else if (out_FrameErrror)
        $display("Frame Error");
     else
        $display("Receiver data %h", out_Data);
  end

endmodule