代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/391531/2519432
cpp xsimtestbench_arch.cpp
#include "work/qwe/testbench_arch.h"
static const char * HSimCopyRightNotice = "Copyright 2004-2005, Xilinx Inc. All rights reserved.";
#include "C:/Xilinx/vhdl/hdp/ieee/std_logic_1164/std_logic_116
www.eeworm.com/read/387424/8683900
vhd tb_progprom_tmpl.vhd
-- VHDL testbench template generated by SCUBA ispLever_v70_SP2_Build (24)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity tb is
end entity tb;
architecture test o
www.eeworm.com/read/423217/10579079
bak test.v.bak
module testbench1();
reg Clk,Reset;
wire BitWire;
reg [3:0] ClkCounter;
reg in_DataEnable;
reg [7:0] in_Data;
wire [7:0] out_Data;
//connect transmitter and receiver
transmitter DUT1(.in_clk(Cl
www.eeworm.com/read/329969/12922928
vhd tb_fifo_dc_tmpl.vhd
-- VHDL testbench template generated by SCUBA ispLever_v70_SP2_Build (24)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity tb is
end entity tb;
architecture test o
www.eeworm.com/read/314053/13576248
vhd simtut_tb.vhd
-- J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\SIMTUT_TB.VHD
-- VHDL testbench created by
-- Xilinx's StateBench 1.01
-- Sat Oct 26 14:36:48 2002
LIBRARY ieee;
USE ieee.std_logic_1164.all;
L
www.eeworm.com/read/314053/13576252
vhd tut_tb.vhd
-- J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\TUT_TB.VHD
-- VHDL testbench created by
-- Xilinx's StateBench 1.01
-- Sat Oct 26 14:41:18 2002
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBR
www.eeworm.com/read/314053/13576256
vhd simtut_tb.vhd
-- J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\SIMTUT_TB.VHD
-- VHDL testbench created by
-- Xilinx's StateBench 1.01
-- Sat Oct 26 14:36:48 2002
LIBRARY ieee;
USE ieee.std_logic_1164.all;
L
www.eeworm.com/read/314053/13576258
vhd tut_tb.vhd
-- J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\TUT_TB.VHD
-- VHDL testbench created by
-- Xilinx's StateBench 1.01
-- Sat Oct 26 14:41:18 2002
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBR
www.eeworm.com/read/310679/13647134
vhd simtut_tb.vhd
-- J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\SIMTUT_TB.VHD
-- VHDL testbench created by
-- Xilinx's StateBench 1.01
-- Sat Oct 26 14:36:48 2002
LIBRARY ieee;
USE ieee.std_logic_1164.all;
L
www.eeworm.com/read/310679/13647136
vhd tut_tb.vhd
-- J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\TUT_TB.VHD
-- VHDL testbench created by
-- Xilinx's StateBench 1.01
-- Sat Oct 26 14:41:18 2002
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBR