代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/359647/10131843
v fsm_example_tb.v
//===== Finite State Machine Example =====
//----- Testbench -----
// Timescale: one time unit = 1ns (e.g., delay specification of #42 means 42ns of time), and
// simulator resolution is 0.1 ns
www.eeworm.com/read/359647/10131848
v fsm_example2_tb.v
//===== Finite State Machine Example =====
//----- Testbench -----
// Timescale: one time unit = 1ns (e.g., delay specification of #42 means 42ns of time), and
// simulator resolution is 0.1 ns
www.eeworm.com/read/278084/10575866
vhd 33_simu.vhd
-- Author : yzf
-- Created On: Thu Dec 21 09:46:16 1995
-- Testbench for comp.comp
architecture BENCH of test_comp is
component comp
PORT(
A: IN SHORT;
B: IN SHORT;
IN_READY:
www.eeworm.com/read/449295/7509155
v fifo_tb.v
//* This automatically generated file is a part of Verilog testbench.
//* This file was generated by Active-HDL 4.2 (TB_verilog v.1.1).
//* Copyright (C) ALDEC Inc.
//* This Verilog file contai
www.eeworm.com/read/298172/7971777
v fifotb.v
// testbench of fifo.v
//date:2005/6/3
//the file name:fifotb.v
//-----------------------------------------------------
module test_fifo;
reg clk;
reg rstp;
reg[15:0] din;
reg readp;
www.eeworm.com/read/332842/12722140
v fifotb.v
// testbench of fifo.v
//date:2005/6/3
//the file name:fifotb.v
//-----------------------------------------------------
module test_fifo;
reg clk;
reg rstp;
reg[15:0] din;
reg readp;
www.eeworm.com/read/316450/13522569
vhd 33_simu.vhd
-- Author : yzf
-- Created On: Thu Dec 21 09:46:16 1995
-- Testbench for comp.comp
architecture BENCH of test_comp is
component comp
PORT(
A: IN SHORT;
B: IN SHORT;
IN_READY:
www.eeworm.com/read/347629/11653490
vhd 33_simu.vhd
-- Author : yzf
-- Created On: Thu Dec 21 09:46:16 1995
-- Testbench for comp.comp
architecture BENCH of test_comp is
component comp
PORT(
A: IN SHORT;
B: IN SHORT;
IN_READY:
www.eeworm.com/read/153614/12021427
vhd 33_simu.vhd
-- Author : yzf
-- Created On: Thu Dec 21 09:46:16 1995
-- Testbench for comp.comp
architecture BENCH of test_comp is
component comp
PORT(
A: IN SHORT;
B: IN SHORT;
IN_READY:
www.eeworm.com/read/151305/12220813
vhd 33_simu.vhd
-- Author : yzf
-- Created On: Thu Dec 21 09:46:16 1995
-- Testbench for comp.comp
architecture BENCH of test_comp is
component comp
PORT(
A: IN SHORT;
B: IN SHORT;
IN_READY: