代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/339051/12265632
txt gencrc.v.txt
//
// Behavioral Verilog for CRC16 and CRC32 for use in a testbench.
//
// The specific polynomials and conventions regarding bit-ordering etc.
// are specific to the Cable Modem DOCSIS protocol,
www.eeworm.com/read/233163/14165929
v tb_fifo.v
/********************************************
A testbench for 8x16 fifo controller.
********************************************/
`timescale 1ns/10ps
module tb_fifo;
reg clk,rst, rd, wr;
r
www.eeworm.com/read/206041/15302066
txt gencrc.v.txt
//
// Behavioral Verilog for CRC16 and CRC32 for use in a testbench.
//
// The specific polynomials and conventions regarding bit-ordering etc.
// are specific to the Cable Modem DOCSIS protocol,
www.eeworm.com/read/13605/279588
txt gencrc.v.txt
//
// Behavioral Verilog for CRC16 and CRC32 for use in a testbench.
//
// The specific polynomials and conventions regarding bit-ordering etc.
// are specific to the Cable Modem DOCSIS protocol,
www.eeworm.com/read/18563/794169
tf test_fixture.tf
module testbench();
// DATE: Wed Nov 06 11:18:34 2002
// TITLE:
// MODULE: top
// DESIGN: top
// FILENAME: top
// PROJECT: dpram_core_demo
// VERSION: Version
// Input
www.eeworm.com/read/32161/1032454
txt gencrc.v.txt
//
// Behavioral Verilog for CRC16 and CRC32 for use in a testbench.
//
// The specific polynomials and conventions regarding bit-ordering etc.
// are specific to the Cable Modem DOCSIS protocol,
www.eeworm.com/read/38898/1117582
txt gencrc.v.txt
//
// Behavioral Verilog for CRC16 and CRC32 for use in a testbench.
//
// The specific polynomials and conventions regarding bit-ordering etc.
// are specific to the Cable Modem DOCSIS protocol,
www.eeworm.com/read/343627/3218664
tf test_fixture.tf
module testbench();
// DATE: Wed Nov 06 11:18:34 2002
// TITLE:
// MODULE: top
// DESIGN: top
// FILENAME: top
// PROJECT: dpram_core_demo
// VERSION: Version
// Input
www.eeworm.com/read/154076/5643053
tf test_fixture.tf
module testbench();
// DATE: Wed Nov 06 11:18:34 2002
// TITLE:
// MODULE: top
// DESIGN: top
// FILENAME: top
// PROJECT: dpram_core_demo
// VERSION: Version
// Input
www.eeworm.com/read/109798/15548363
txt gencrc.v.txt
//
// Behavioral Verilog for CRC16 and CRC32 for use in a testbench.
//
// The specific polynomials and conventions regarding bit-ordering etc.
// are specific to the Cable Modem DOCSIS protocol,