test_fixture.tf

学习Xilinx公司开发软件ISE的基础资料

module testbench();

// DATE:     Wed Nov 06 11:18:34 2002 
// TITLE:    
// MODULE:   top
// DESIGN:   top
// FILENAME: top
// PROJECT:  dpram_core_demo
// VERSION:  Version


// Inputs
    reg [3:0] addra;
    reg [3:0] addrb;
    reg clka;
    reg clkb;
    reg [15:0] dina;
    reg [15:0] dinb;
    reg wea;
    reg web;


// Outputs
    wire [15:0] douta;
    wire [15:0] doutb;


// Bidirs


// Instantiate the UUT
    top uut (
        .addra(addra), 
        .addrb(addrb), 
        .clka(clka), 
        .clkb(clkb), 
        .dina(dina), 
        .dinb(dinb), 
        .douta(douta), 
        .doutb(doutb), 
        .wea(wea), 
        .web(web)
        );


// Initialize Inputs
    `ifdef auto_init

        initial begin
            addra = 0;
            addrb = 0;
            clka = 0;
            clkb = 0;
            dina = 0;
            dinb = 0;
            wea = 0;
            web = 0;
        end

    `endif


endmodule