代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/169316/9867215
txt readme.txt
AD
++++++++++++++++++++++++++
RS Decoder (31,19,6) v1.1
++++++++++++++++++++++++++
This project consists of 8 verilog files including a testbench file.
The files are:
- RSDecoder.v : contains
www.eeworm.com/read/273124/10925420
h resource.h
//{{NO_DEPENDENCIES}}
// Microsoft Developer Studio generated include file.
// Used by TestBench.rc
//
#define IDD_ABOUTBOX 100
#define IDR_MAINFRAME 128
#de
www.eeworm.com/read/457417/7325726
vhd analytic_filter_tb.vhd
-- Testbench for Filters H_a1-4(z)
-- Uses a sine sweep as stimuli
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
www.eeworm.com/read/260328/4334281
tcl sdr_tsim.tcl
cd ../timing
if {![file exists work]} {
vlib work
}
vmap work work
# compile all necessary source and testbench files
#
# Start compiling.............
vlog ../../../../par/xm/sdr_
www.eeworm.com/read/193880/8203791
txt readme.txt
++++++++++++++++++++++++++
RS Decoder (31,19,6) v1.1
++++++++++++++++++++++++++
This project consists of 8 verilog files including a testbench file.
The files are:
- RSDecoder.v : contains descriptio
www.eeworm.com/read/300556/13906112
txt readme.txt
++++++++++++++++++++++++++
RS Decoder (31,19,6) v1.1
++++++++++++++++++++++++++
This project consists of 8 verilog files including a testbench file.
The files are:
- RSDecoder.v : contains descriptio
www.eeworm.com/read/364127/9921610
v freqdiv_tb.v
// Parameterizable Frequency Divider -- Testbench
//
// Ed Doering
// 29 Feb 2004
//
module Frequency_Divider_TB;
reg Clock;
reg Reset;
wire Out;
// Instantiate the device
Frequency_Di
www.eeworm.com/read/273124/10925436
cpp testbenchview.cpp
// TestBenchView.cpp : implementation of the CTestBenchView class
//
#include "stdafx.h"
#include "TestBench.h"
#include "TestBenchDoc.h"
#include "TestBenchView.h"
#ifdef _DEBUG
#define
www.eeworm.com/read/330692/12874703
txt gencrc.v.txt
//
// Behavioral Verilog for CRC16 and CRC32 for use in a testbench.
//
// The specific polynomials and conventions regarding bit-ordering etc.
// are specific to the Cable Modem DOCSIS protocol,
www.eeworm.com/read/339051/12264566
txt gencrc.v.txt
//
// Behavioral Verilog for CRC16 and CRC32 for use in a testbench.
//
// The specific polynomials and conventions regarding bit-ordering etc.
// are specific to the Cable Modem DOCSIS protocol,