sdr_tsim.tcl

使用FPGA做SDRAM控制器

cd ../timing

if {![file exists work]} {
     vlib work
}

vmap work work

# compile all necessary source and testbench files
#

# Start compiling.............
vlog ../../../../par/xm/sdr_top.vo 

vlog +incdir+../../../../source ../../../../testbench/sdr_tb.tf

# End


# Load the top testbench file
vsim -L xp_vlg -sdfmax /UUT=../../../../par/xm/sdr_top.sdf -multisource_delay max work.sdr_tb

add wave -r /*

run -all