代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/145015/12756145
v mypli.v
// Simple VCS PLI example.
//
// The testbench 'test' instantiates a submodule called 'stub' which is a wrapper around the
// embedded PLI model.
//
module test;
// Testbench I/O
reg clk;
reg reset
www.eeworm.com/read/7866/137501
do wave_color.do
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -color Red -format Logic /testbench/reset
add wave -noupdate -color Orange -format Logic /testbench/clk
add wave -noupdate -co
www.eeworm.com/read/32732/1035942
do wave.do
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -color Red -format Logic /testbench/reset
add wave -noupdate -color Orange -format Logic /testbench/clk
add wave -noupdate -co
www.eeworm.com/read/40446/1139360
do wave.do
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -color Red -format Logic /testbench/reset
add wave -noupdate -color Orange -format Logic /testbench/clk
add wave -noupdate -co
www.eeworm.com/read/480257/1320653
do wave_abc_user.do
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {APB Bus}
add wave -noupdate -format Logic /TESTBENCH/UUT/PCLK
add wave -noupdate -format Logic /TESTBENCH/UUT/PR
www.eeworm.com/read/397063/2404604
do rsdecoder.do
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Literal /testbench_rsdecoder/rsdecoder/recword
add wave -noupdate -format Logic /testbench_rsdecoder/rsdecoder/clock1
www.eeworm.com/read/397063/2404605
do csee1.do
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Literal /testbench_rsdecoder/rsdecoder/recword
add wave -noupdate -format Logic /testbench_rsdecoder/rsdecoder/clock1
www.eeworm.com/read/397063/2404606
do kes.do
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /testbench_rsdecoder/rsdecoder/KESblock/active_kes
add wave -noupdate -format Logic /testbench_rsdecoder/rsdecode
www.eeworm.com/read/464847/7060900
vhd test_comblock.vhd
library ieee;
use ieee.std_logic_1164.all;
entity testbench is
end testbench;
architecture v1 of testbench is
-- Inputs
signal clock, clear : std_logic;
signal SW0, SW1, SW2, SW3, SW4, SW5, SW6,
www.eeworm.com/read/430383/8751976
vhd compressor_tb.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : JPEG Hardware Compressor Testbench
-- Design : jpeg
-- Author : Victor