代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/163678/10150664
cpp eval_update.cpp
//BEGIN eval_update/eval_update.cpp
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//See eval_update.h for a details.
#include "eval_update.h"
void Eval_Update::Q1_m
www.eeworm.com/read/281220/10255885
do wave_post.do
onerror {resume}
quietly WaveActivateNextPane {} 0
quietly virtual signal -install /testbench/cf_plus_top { (context /testbench/cf_plus_top )(cf_plus_logic_soft_reset & level_pulse_n & cf_plus_logic
www.eeworm.com/read/462030/7212064
vhd test.vhd
-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for th
www.eeworm.com/read/457876/7316234
vhd tb_fir.vhd
-- ================================================================================
-- Legal Notice: Copyright (C) 1991-2006 Altera Corporation
-- Any megafunction design, and related net list (encryp
www.eeworm.com/read/329969/12922686
vhd getpcm_t.vhd
-- VHDL Test Bench Created from source file GetPcm.vhd -- 06/19/08 19:50:10
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_v
www.eeworm.com/read/329969/12922749
bak getpcm_t.vhd.bak
-- VHDL Test Bench Created from source file GetPcm.vhd -- 06/19/08 19:50:10
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_v
www.eeworm.com/read/215073/15075591
vhd test.vhd
-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for th
www.eeworm.com/read/168399/5447248
do ac97_if.do
vsim TESTBENCH_ac97_if
add wave fast_clk bit_clk sdata_out sdata_in
#add wave uut/ac97_if_i/command_SM uut/ac97_if_i/codec_rdy
#add wave uut/ac97_if_i/command_num
#add wave -hex uut/ac97_if_i/
www.eeworm.com/read/168399/5447268
do standalone.do
vsim TESTBENCH_standalone
add wave fast_clk reset_n bit_clk sdata_out sdata_in Sync
add wave uut/ac97_if_i/command_SM uut/ac97_if_i/codec_rdy
add wave uut/ac97_if_i/command_num
add wave -hex u
www.eeworm.com/read/154076/5643168
transcript
# Reading J:/eda/Modeltech_5.5f/win32/../tcl/vsim/pref.tcl
# do alu_tst_wave.fdo
# Model Technology ModelSim SE vlog 5.5f Compiler 2002.01 Jan 7 2002
# -- Compiling module alu
# Top level modul