getpcm_t.vhd

PCM数据采集

-- VHDL Test Bench Created from source file GetPcm.vhd -- 06/19/08  19:50:10
--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Lattice recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "source->import"
-- menu in the ispLEVER Project Navigator to import the testbench.
-- Then edit the user defined section below, adding code to generate the 
-- stimulus for your design.
-- 3) VHDL simulations will produce errors if there are Lattice FPGA library 
-- elements in your design that require the instantiation of GSR, PUR, and
-- TSALL and they are not present in the testbench. For more information see
-- the How To section of online help.  
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	COMPONENT GetPcm
	PORT(
		Reset : IN std_logic;
		Clock : IN std_logic;
		Uart_In : IN std_logic;
		PCM_CLK : IN std_logic;
		PCM_Fsync : IN std_logic;
		PCM_Din : IN std_logic;
		PCM_Dout : IN std_logic;          
		Uart_Out : OUT std_logic
		);
	END COMPONENT;

	SIGNAL Reset :  std_logic := '0';
	SIGNAL Clock :  std_logic := '0';
	SIGNAL Uart_In :  std_logic := '1';
	SIGNAL Uart_Out :  std_logic := '1';
	SIGNAL PCM_CLK :  std_logic := '0';
	SIGNAL PCM_Fsync :  std_logic := '0';
	SIGNAL PCM_Din :  std_logic := '0';
	SIGNAL PCM_Dout :  std_logic := '1';

BEGIN

	uut: GetPcm PORT MAP(
		Reset => Reset,
		Clock => Clock,
		Uart_In => Uart_In,
		Uart_Out => Uart_Out,
		PCM_CLK => PCM_CLK,
		PCM_Fsync => PCM_Fsync,
		PCM_Din => PCM_Din,
		PCM_Dout => PCM_Dout
	);


-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
   Reset <= '0';
   wait for 100 ns;
   Reset <= '1';
      wait; -- will wait forever
   END PROCESS;
   
   process
   begin
   wait until PCM_CLK = '1';
   PCM_Din <= not PCM_Din;
   PCM_Dout <= not PCM_Dout;
   end process;
   
   process
   begin
   wait until PCM_CLK = '1';
   PCM_Fsync <= '1' after 2 ns;
   wait until PCM_CLK = '1';
   PCM_Fsync <= '0' ;
   wait for 124390 ns;
   end process;
   
   PCM_CLK <= not PCM_CLK after 244 ns;
   Clock <=not Clock after 15259 ps;
-- *** End Test Bench - User Defined Section ***

END;