代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/443860/7621451
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_testbench is
generic(
tp : integer := 1;
brp : integer := 4
);
end can_testbench;
www.eeworm.com/read/297458/8016489
do wave.do
onerror {resume}
quietly WaveActivateNextPane {} 0
virtual type { LMR ARF PCH ACT WR RD BT NOP} CmdType
quietly set wcmd "virtual function -install /${testbench_name}/dut/ { (CmdType)&{/${testbench_n
www.eeworm.com/read/332094/12781015
txt fpga验证.txt
FPGA验证简介(1)
以前帖过，好像丢了（edacn好像丢了不少好的旧贴，真可惜），昨天网友提出重贴，所以今天就把他再发一次，反正不用交"版面费"，哈哈
注：本文为edacn.net特约创作，转载请注明出处。
第一编 验证的重要性
验证，顾名思义就是通过仿真、时序分析、上板调试等手段检验设计正确性的过程，在FPGA/IC开发流程中，验证主要包括功能验证和时序验证两个部分。为了了 ...
www.eeworm.com/read/309919/13661941
vhd txmit_tb.vhd
-- VHDL Test Bench Created from source file txmit.vhd -- 16:58:29 04/12/2000
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_v
www.eeworm.com/read/480672/6659794
transcript
# Reading C:/Modeltech_6.0/tcl/vsim/pref.tcl
# // ModelSim SE 6.0 Aug 19 2004
# //
# // Copyright Mentor Graphics Corporation 2004
# // All Rights Reserved.
# //
# // THIS WORK
www.eeworm.com/read/345047/11844704
do wave.do
onerror {resume}
quietly WaveActivateNextPane {} 0
virtual type { LMR ARF PCH ACT WR RD BT NOP} CmdType
quietly set wcmd "virtual function -install /${testbench_name}/dut/ { (CmdType)&{/${testben
www.eeworm.com/read/345045/11845217
do wave.do
onerror {resume}
quietly WaveActivateNextPane {} 0
virtual type { LMR ARF PCH ACT WR RD BT NOP} CmdType
quietly set wcmd "virtual function -install /${testbench_name}/dut/ { (CmdType)&{/${testben
www.eeworm.com/read/118540/14864326
vhd test_tb.vhd
-- VHDL Test Bench Created from source file test.vhd -- 19:28:26 09/23/2002
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the
www.eeworm.com/read/168399/5447269
do ac97_core.do
# Simulation environment for testbench_ac97_core
vsim work.testbench_ac97_core
add wave test_no
############################################################
### AC97_core signals
##########
www.eeworm.com/read/473137/6856870
vhd txmit_tb.vhd
-- VHDL Test Bench Created from source file txmit.vhd -- 16:58:29 04/12/2000
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_v