test_tb.vhd

用vhdl实现ps2鼠标的源程序

-- VHDL Test Bench Created from source file test.vhd -- 19:28:26 09/23/2002
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	COMPONENT test
	PORT(
		reset : IN std_logic;
		clk : IN std_logic;
		ps2_clk : IN std_logic;          
		rise : OUT std_logic;
		fall : OUT std_logic
		);
	END COMPONENT;

	SIGNAL reset :  std_logic;
	SIGNAL clk :  std_logic;
	SIGNAL ps2_clk :  std_logic;
	SIGNAL rise :  std_logic;
	SIGNAL fall :  std_logic;

BEGIN

	uut: test PORT MAP(
		reset => reset,
		clk => clk,
		ps2_clk => ps2_clk,
		rise => rise,
		fall => fall
	);


	PROCESS -- clock process
	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 4 ns;
		clk <= transport '1';
		WAIT FOR 4 ns;
		WAIT FOR 16 ns;
		clk <= transport '0';
		WAIT FOR 16 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	process
	begin
	  reset <= transport '0';
	  wait for 30 ns;
	  reset <= transport '1';
	  wait;
	end process;

	PROCESS -- ps/2 clock process
	BEGIN
		CLOCK_LOOP : LOOP
		ps2_clk <= transport '0';
		WAIT FOR 8 ns;
		ps2_clk <= transport '1';
		WAIT FOR 8 ns;
		WAIT FOR 160 ns;
		ps2_clk <= transport '0';
		WAIT FOR 160 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;
-- *** Test Bench - User Defined Section ***
   --tb : PROCESS
   --BEGIN
    --  wait; -- will wait forever
   --END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;