代码搜索：system verilog
找到约 10,000 项符合「system verilog」的源代码
代码结果 10,000
www.eeworm.com/read/18028/771264
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c12
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym
www.eeworm.com/read/18028/771265
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:41:20 10/02/2007
// Design Name:
/
www.eeworm.com/read/18028/771266
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c12
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym
www.eeworm.com/read/20129/832926
verilog
www.eeworm.com/read/40125/1138487
verilog
www.eeworm.com/read/40490/1139801
verilog
www.eeworm.com/read/349103/10851361
syn top%verilog__verilog.syn
www.eeworm.com/read/349103/10851508
syn example%verilog__verilog.syn
www.eeworm.com/read/285475/8837669
system
www.eeworm.com/read/378355/9235101