代码搜索：sync
找到约 6,244 项符合「sync」的源代码
代码结果 6,244
www.eeworm.com/read/271650/4227095
h funresourcesp.h
//{{NO_DEPENDENCIES}}
// Microsoft Visual C++ generated include file.
// Used by FunLanguagesp.rc
//
#define IDS_CARDVIEW_SYNC 3
#define IDS_ENABLE_COMPRESSION 4
#define I
www.eeworm.com/read/427629/1968887
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity dcfifo_sync is
generic(
lpm_width : integer := 1;
lpm_widthu : integer := 1;
lpm_numwords : integer := 2;
www.eeworm.com/read/427629/1968993
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity dcfifo_sync is
generic(
lpm_width : integer := 1;
lpm_widthu : integer := 1;
lpm_numwords : integer := 2;
www.eeworm.com/read/427629/1969129
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity dcfifo_sync is
generic(
lpm_width : integer := 1;
lpm_widthu : integer := 1;
lpm_numwords : integer := 2;
www.eeworm.com/read/427629/1969270
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity dcfifo_sync is
generic(
lpm_width : integer := 1;
lpm_widthu : integer := 1;
lpm_numwords : integer := 2;
www.eeworm.com/read/426010/1997104
changelog
Build
-- Hold lock when creating new H.323 channel to sync the audio channels
-- Decrement usage counter when appropriate
-- Actually unregister everything in unload_module
-- Add IP based authent
www.eeworm.com/read/398634/2375246
test rpl_ps.test
#
# Test of replicating user variables
#
source include/master-slave.inc;
#save_master_pos;
#connection slave;
#sync_with_master;
#reset master;
#connection master;
--disable_warnings
drop table if
www.eeworm.com/read/396408/2420002
h help_mp-sv.h
// Last sync on 2004-10-20 with help_mp-en.h 1.148
// Translated by: Carl Fürstenberg
// Helped by: Jan Knutar
// ========================= MPlayer
www.eeworm.com/read/386605/2569927
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity dcfifo_sync is
generic(
lpm_width : integer := 1;
lpm_widthu : integer := 1;
lpm_numwords : integer := 2;
www.eeworm.com/read/381853/2640106
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity dcfifo_sync is
generic(
lpm_width : integer := 1;
lpm_widthu : integer := 1;
lpm_numwords : integer := 2;