代码搜索：sync
找到约 6,244 项符合「sync」的源代码
代码结果 6,244
www.eeworm.com/read/139207/5806561
h dcapte.h
/* Beholder RMON ethernet network monitor,Copyright (C) 1993 DNPAP group */
/* See file COPYING 'GNU General Public Licence' for copyright details */
#ifndef _DCAPTUREE_H
#define _DCAPTUREE_H
enum
www.eeworm.com/read/136989/5834256
cpp messaging_orbinitializer.cpp
// -*- C++ -*-
#include "Messaging_ORBInitializer.h"
#include "Messaging_Policy_i.h"
#include "Connection_Timeout_Policy_i.h"
#include "Messaging_PolicyFactory.h"
#include "tao/ORB_Core.h"
www.eeworm.com/read/127781/5997045
makefile
# arch/i386/oprofile/Makefile
O_TARGET:=oprofile.o
obj-m := $(O_TARGET)
obj-y := init.o timer_int.o \
$(addprefix ../../../drivers/oprofile/, \
oprof.o cpu_buffer.o buffer_sync.o
www.eeworm.com/read/492414/6422483
m receiver.m
%Receiver
function [data_bits, rx_bits] = receiver(rx_signal, cir, sys_parm)
%Packet search
[rx_signal, thres_idx] = rx_find_packet_edge(rx_signal, sys_parm);
%Frequency erro
www.eeworm.com/read/406417/11442820
conf storage2.conf
disabled=false
group_name=group2
bind_addr=
port=23001
network_timeout=20
heart_beat_interval=30
stat_report_interval=60
base_path=/home/yuqing/FastDFS2
sync_wait_msec=200
tracker_server=10.62.245.1
www.eeworm.com/read/337834/12338905
am makefile.am
## Process this file with automake to produce Makefile.in
## Do not edit this file directly. It is generated from Makefile.am.m4
SUFFIXES = .x .C .h .py
.x.h:
-$(RPCC) -h -DSFSSVC $< || rm -f $@
.
www.eeworm.com/read/217049/14980857
c bugs.c
/*
bugs.c
fix_bugs()
*/
#include
#include
#include
#include
/* non-standard includes... */
#include
#include
#includ
www.eeworm.com/read/159314/5586121
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity c_gate_bit_bus_v5_0 is
generic(
c_ainit_val : string := "";
c_enable_rlocs : integer := 1;
c_gate_type : integer
www.eeworm.com/read/159314/5586215
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity c_gate_bit_bus_v4_0 is
generic(
c_ainit_val : string := "";
c_enable_rlocs : integer := 1;
c_gate_type : integer
www.eeworm.com/read/159314/5586308
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity c_gate_bit_bus_v2_0 is
generic(
c_ainit_val : string := "";
c_enable_rlocs : integer := 1;
c_gate_type : integer