代码搜索:sync

找到约 6,244 项符合「sync」的源代码

代码结果 6,244
www.eeworm.com/read/459541/7274020

h sdhal.h

#ifndef SDHSL_H #define SDHSL_H #include void init_spi1(); void CloseSPI( void ); void SPI_SendByte(char byte); char SPI_RecByte(void); void SPI_CS_Assert(void); v
www.eeworm.com/read/443860/7621448

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity can_register_asyn_syn is generic( width : integer := 8; reset_value : integer := 0 ); port( data_in
www.eeworm.com/read/142740/12923957

c main.c

/** \file USBisp main Autor: Matthias Wei遝r Copyright 2004: Matthias Wei遝r License: QPL (see license.txt) */ /*! \mainpage USBisp (c)2004 by Matthias Weisser
www.eeworm.com/read/141297/5773639

h gr_complex_to_xxx.h

/* -*- c++ -*- */ /* * Copyright 2004 Free Software Foundation, Inc. * * This file is part of GNU Radio * * GNU Radio is free software; you can redistribute it and/or modify * it under the ter
www.eeworm.com/read/136989/5838349

cpp syncscope_setup.cpp

/** * @file SyncScope_Setup.cpp * * SyncScope_Setup.cpp,v 1.5 2002/03/04 17:13:29 coryan Exp * * @author Carlos O'Ryan */ #include "SyncScope_Setup.h" #include "RIR_Na
www.eeworm.com/read/488668/6483451

c main.c

/** \file USBisp main Autor: Matthias Wei遝r Copyright 2004: Matthias Wei遝r License: QPL (see license.txt) */ /*! \mainpage USBisp (c)2004 by Matthias Weisser
www.eeworm.com/read/225681/14525936

v dac7512.v

module DAC7512 (BlockSel, RegSel, CPUWR, CPUClock, DIn, SYNC_n, SIn, TxD_OE, Reset); input BlockSel; input RegSel; input CPUWR; input CP
www.eeworm.com/read/118214/14881617

h pes.h

/* * ISO 13818 stream multiplexer * Copyright (C) 2001 Convergence Integrated Media GmbH Berlin * Author: Oskar Schirmer (schirmer@scara.com) * * This program is free software; you can redistribu
www.eeworm.com/read/159314/5586201

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity mac_delay_control_v1_1_v is generic( c_a_type : integer := 0; c_a_width : integer := 1; c_b_mode : int
www.eeworm.com/read/159314/5586297

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity mac_delay_control_v1_0_v is generic( c_a_type : integer := 0; c_a_width : integer := 1; c_b_mode : int