代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/325319/13212433
tb uart.tb
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY TestBench IS
END TestBench;
ARCHITECTURE HTWTestBench OF TestBench IS
COMPONENT ua
www.eeworm.com/read/325319/13212443
vhd uart.vhd
--/*******************************************************************
-- *
-- * DESCRIPTION: UART top level module implements full duplex UART function.
-- *
-- * AUTHOR: Jim Jian
-- *
-
www.eeworm.com/read/240364/13221587
vhd idt.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity IDT is
port(clk:in std_logic;
ctrl:in std_logic;
ce,Rd,oe:out
www.eeworm.com/read/138605/13228497
vhd i60bcd.vhd
--The IEEE standard 1164 package, declares std_logic, rising_edge(), etc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity i60bcd i
www.eeworm.com/read/138605/13228523
vhd regne.vhd
--regne.vhd n-bit register with enable
library ieee ;
use ieee.std_logic_1164.all ;
entity regne is
generic ( n : integer := 12 ) ;
port (
r : in std_logic_vector(n-1 downto 0) ;--register
www.eeworm.com/read/138605/13228578
vhd negative.vhd
--negative.vhd correct negative number circuit
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity negative is
port(
a : in std_logic_vector(11 downto 0);--块
www.eeworm.com/read/138605/13228604
vhd bcdadd.vhd
--bcdadd.vhd 1 digit bcd adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcdadd is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/138605/13228613
vhd bcd.vhd
--bcd.vhd 1 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/138605/13228623
vhd multiplier.vhd
--multiplier.vhd n-bit multiplier
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity multiplier is
generic ( n : integer := 7; nn :
www.eeworm.com/read/138605/13228640
vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆