idt.vhd

来自「基于51单片机的双口RAMIDT7131的驱动程序」· VHDL 代码 · 共 37 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity IDT is
    port(clk:in std_logic;
        ctrl:in std_logic;
    ce,Rd,oe:out std_logic; 
        addr:out std_logic_vector(10 downto 0)
        );
end entity IDT;

architecture one of IDT is
    signal cnt:std_logic_vector(14 downto 0);
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if ctrl='1' then
                 cnt<=cnt+1;
                 oe<='0';
                 rd<='1';
                 ce<='0'; 
             else
                 cnt<=(others=>'0');
                 ce<='1';
             end if;
        end if;
    end process;
    addr<=cnt(14 downto 4);
end architecture one;