代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/139313/13163437
vhd div.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div is
port(clk: in std_logic;
dataout: out std_logic_vector(4 downto 0));
end div;
architectu
www.eeworm.com/read/139313/13163467
vhd divid.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity divid is
port (testin:in std_logic_vector(4 downto 0);
datain:in std_logic_vector(7 downto 0);
test
www.eeworm.com/read/326024/13169738
vhd cnt8.vhd
LIBRARY IEEE; -- 8进制计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT8 IS
PORT ( CLK : IN STD_LOGIC;
CQ : OU
www.eeworm.com/read/326024/13169857
vhd cnt5.vhd
LIBRARY IEEE; -- 4进制计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT5 IS
PORT ( CLK : IN STD_LOGIC;
AA : OU
www.eeworm.com/read/326024/13169865
vhd dec1.vhd
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Dec1 IS
PORT ( CLK : IN STD_LOGIC;
D : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END ;
ARCH
www.eeworm.com/read/326024/13169882
vhd cnt2.vhd
LIBRARY IEEE; -- 4进制计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT2 IS
PORT ( CLK : IN STD_LOGIC;
CQ : OU
www.eeworm.com/read/326024/13169911
vhd decd.vhd
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DECD IS
PORT ( CLK : IN STD_LOGIC;
DSPY : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
D :
www.eeworm.com/read/240992/13180266
m uwb_sv_params.m
function [Lam,lambda,Gam,gamma,std_ln_1,std_ln_2,nlos,std_shdw] = uwb_sv_params( cm_num )
% Return S-V model parameters for standard UWB channel models
% Lam Cluster arrival rate (clusters per ns
www.eeworm.com/read/240992/13180331
m uwb_sv_params.m
function [Lam,lambda,Gam,gamma,std_ln_1,std_ln_2,nlos,std_shdw] = uwb_sv_params( cm_num )
% Return S-V model parameters for standard UWB channel models
% Lam Cluster arrival rate (clusters per ns
www.eeworm.com/read/325800/13184097
vhd addr.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity addr is
port (
a: in STD_LOGIC;
b: in STD_LOGIC;
ci: in STD_LOGIC;
sum: out STD_LOGIC;
co: out S