div.vhd

来自「一個LCD燈的小程序。不是我寫的。我只負責了調試。適用在ACEXEP1K30QC」· VHDL 代码 · 共 23 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div is
port(clk:      in    std_logic;
     dataout:  out   std_logic_vector(4 downto 0));
end div;
architecture alfa of div is
  signal count: std_logic_vector(21 downto 0);
begin
  dataout(0)<=count(8);
  dataout(1)<=count(18);
  dataout(2)<=count(19);
  dataout(3)<=count(20);
  dataout(4)<=count(21);
process(clk)
  begin
    if count="1111111111111111111111" then count<="0000000000000000000000"; 
      elsif clk'event and clk='1' then
        count<=count+1;
          end if;
end process;
end architecture;