📄 div.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div is
port(clk: in std_logic;
dataout: out std_logic_vector(4 downto 0));
end div;
architecture alfa of div is
signal count: std_logic_vector(21 downto 0);
begin
dataout(0)<=count(8);
dataout(1)<=count(18);
dataout(2)<=count(19);
dataout(3)<=count(20);
dataout(4)<=count(21);
process(clk)
begin
if count="1111111111111111111111" then count<="0000000000000000000000";
elsif clk'event and clk='1' then
count<=count+1;
end if;
end process;
end architecture;
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