代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/333222/12696941
vhd idt723626.vhd
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-- Copyri
www.eeworm.com/read/333222/12696976
vhd idt723622.vhd
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-- File name : idt723622.vhd
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-- Copyri
www.eeworm.com/read/333222/12697213
vhd cy7c199.vhd
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-- File Name: cy7c199.vhd
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-- Copyrig
www.eeworm.com/read/333222/12697305
vhd cy7c195.vhd
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-- File Name: cy7c195.vhd
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-- Copyrig
www.eeworm.com/read/333222/12697331
vhd cy7c166.vhd
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-- File Name: cy7c166.vhd
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-- Copyrig
www.eeworm.com/read/333222/12697364
vhd cy7c109.vhd
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-- File Name: cy7c109.vhd
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-- Copyrig
www.eeworm.com/read/246676/12713329
vhd reg_32bit.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity reg_32bit is
port(load:in std_logic;
din:in std_logic_vector(31 down
www.eeworm.com/read/246676/12713345
vhd counter_10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter_10 is
port(clk:in std_logic;
clr:in std_logic;
en:
www.eeworm.com/read/246670/12715250
vhd cnt10bcd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cnt10bcd is
Port ( clkin :in std_logic;
co :out std_logic;
qout
www.eeworm.com/read/246188/12752057
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-- Generated Binary Up Counter
-- The first design entity is a T-type flip-flop.
-- The second is an scalable synchronous binary up counter illustrating the use of the generate statement to produce