代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/434564/7859309
vhd bbfifo_16x8.vhd
-- 'Bucket Brigade' FIFO
-- 16 deep
-- 8-bit data
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
www.eeworm.com/read/199424/7860677
vhd v_riscmcu.vhd
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU projec
www.eeworm.com/read/399458/7860791
vhd encoder.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY encoder IS
PORT (e,f,g,h,i,j :IN std_logic;
codeout :OUT std_logic_vector(3 DOWNTO 0)
);
END encoder;
ARCHITECTURE behave
www.eeworm.com/read/399458/7861075
vhd vote7.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY vote7 IS
PORT( men:IN STD_LOGIC_VECTOR(6 downto 0);
LedPass,LedFail: OUT STD_LOGIC);
END vote7;
www.eeworm.com/read/199166/7881153
vhd bbfifo_16x8.vhd
-- 'Bucket Brigade' FIFO
-- 16 deep
-- 8-bit data
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
www.eeworm.com/read/433617/7918543
vhd jishixianshi.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JISHIXIANSHI IS
PORT ( CLK0 ,clk1, EN, RST : IN STD_LOGIC;
SG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
www.eeworm.com/read/198555/7927675
vhd mc8051_clockdiv_.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-----------------------------ENTITY DECLARATION--------------------------------
entity mc8051_clockdiv is
port (clk
www.eeworm.com/read/198555/7927833
vhd control_fsm_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
www.eeworm.com/read/298837/7931807
vhd fulladder_4.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FullAdder_4 IS
PORT(dataA,dataB:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
carryin:IN STD_LOGIC;
sum:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
carryout:OUT S
www.eeworm.com/read/298792/7935271
vhf swepfre.vhf
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
-----------------------------------------------------