代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
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vhd dled.vhd
--1,DLED 时钟总模块
--文件名：DLED.VHD
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DLED is
port (
clk1,clk2: in
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vhd count.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT IS
PORT(CLK,CLR,EN,REBACK: IN STD_LOGIC;
S_1MS: OUT STD_LOGIC_VECTOR(3 D
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vhd mb.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MB IS
PORT(SP,reback,CLR,CLK:IN STD_LOGIC;
CO,EN: OUT STD_LOGIC;
LED: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
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vhd bcd.vhd
--实验3
--BCD码的加法运算
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY bcd IS
PORT( a : UNSIGNED(4 DOWNTO 0);
b : UNSIGNED(4 DOWNTO 0);
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vhd reg10b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG10B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO
www.eeworm.com/read/451632/7461087
vhd reg32b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG32B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO
www.eeworm.com/read/450861/7475527
vhd vote7.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY vote7 is
PORT (men:IN std_logic_vector(6 downto 0);
stop:buffer std_logic);
END vote7;
ARCHITECTURE behave OF
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vhd leon_pci.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library
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vhd pci_oc.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 2003 Gaisler Research
--
-- This library is free soft
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vhd mmutlb.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 2003 Gaisler Research, all rights reserved
--
-- Thi