代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/274276/10879383
vhd bcdadd.vhd
--bcdadd.vhd 1 digit bcd adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcdadd is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/274276/10879387
vhd bcd.vhd
--bcd.vhd 1 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/274276/10879397
vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
www.eeworm.com/read/274168/10886532
vhd memtest.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use WORK.common.all;
use WORK.rand.all;
package mem is
component memTest
generic(
DATA_WIDTH : natura
www.eeworm.com/read/273857/10897442
vhd dual_reg4.vhd
library ieee;
use ieee.std_logic_1164.all;
entity dual_reg4 is
port(a:in std_logic_vector(3 downto 0);
b:in std_logic_vector(3 downto 0);
clk:in std_logic;
lda:in std_
www.eeworm.com/read/273857/10897900
vhd dual_reg4.vhd
library ieee;
use ieee.std_logic_1164.all;
entity dual_reg4 is
port(a:in std_logic_vector(3 downto 0);
b:in std_logic_vector(3 downto 0);
clk:in std_logic;
lda:in std_
www.eeworm.com/read/273857/10898087
vhd dual_reg4.vhd
library ieee;
use ieee.std_logic_1164.all;
entity dual_reg4 is
port(a:in std_logic_vector(3 downto 0);
b:in std_logic_vector(3 downto 0);
clk:in std_logic;
lda:in std_
www.eeworm.com/read/272176/10967521
vhd cnt6.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT6 IS
PORT(CLK: IN STD_LOGIC;
CLR: IN STD_LOGIC;
ENA: IN STD_LOGIC;
CQ: OUT STD_LOGIC_VECTOR(3 DOWNT
www.eeworm.com/read/272176/10967529
vhd pulse.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY PULSE IS
PORT(CLK: IN STD_LOGIC;
A,B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
PSOUT: OUT STD_LOGIC);
END ENTI
www.eeworm.com/read/272176/10967551
vhd time.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TIMES IS
PORT(CLR: IN STD_LOGIC;
CLK: IN STD_LOGIC;
ENA: IN STD_LOGIC;
DOUT: OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END ENT