代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/349548/10819502
vhd jioujiaoyan.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jioujiaoyan is
port(a:in std_logic_vector(7 downto 0);
q:out std_logic);
end
www.eeworm.com/read/349548/10819520
vhd dff.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dff is
port(a :in std_logic;
b :in std_logic;
sel:in std_logic;
c:out
www.eeworm.com/read/349548/10819630
vhd addr.vhd
--addr (模块)正弦
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addr is
port(
clk:in std_logic;
dout:out std_logic_vector(5 downto 0)
);
end ad
www.eeworm.com/read/349548/10819687
vhd sanjiao.vhd
--sanjiao 模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sanjiao is
port(
clk :in std_logic;
dout : out std_logic_vector(5 downto 0)
)
www.eeworm.com/read/349548/10819716
vhd updown2.vhd
-- updown2 模块(of testup_f_k)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity updown2 is
port(
r_in:in std_logic;
www.eeworm.com/read/349548/10819776
vhd decoder_3_8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder_3_8 is
port(a,b,c,e1,e2,e3:in std_logic;
y:out std_logic_vector(7
www.eeworm.com/read/349548/10819797
vhd rom256x8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
LIBRARY work;
USE work.ram_constants.ALL;
ENT
www.eeworm.com/read/349548/10819816
vhd decoder_4_16.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder_4_16 is
port(a1,b1,c1,d1,g2a1,g2b1:in std_logic;
y1,y2:out std_logi
www.eeworm.com/read/419920/10829309
vhd speed.vhd
--16 mtimes;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY speed IS
PORT(
clk,reset,start : IN STD_LOGIC;
k : IN STD_LOGIC_VECTOR(4 downto 0);
clk
www.eeworm.com/read/349383/10831502
vhd dpram.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dpram is
end entity;
architecture Behavioral of dpram is
constant delay : ti