代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/423565/10547560
vhd loadpw.vhd
-----------------------------------------------------------------------------
-- Project Name : NCO
www.eeworm.com/read/278318/10548291
vhd mux21w16.vhd
-- output of CoreGen module generator
-- $Header: mux2VHT.vhd,v 1.2 1998/06/15 17:57:53 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
www.eeworm.com/read/278318/10548330
vhd mux4w16.vhd
-- output of CoreGen module generator
-- $Header: mux4VHT.vhd,v 1.2 1998/06/15 17:58:03 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
www.eeworm.com/read/160189/10559664
vhd compressor_tb.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : JPEG Hardware Compressor Testbench
-- Design : jpeg
-- Author : Victor
www.eeworm.com/read/352343/10562299
m uwb_sv_params.m
function [Lam,lambda,Gam,gamma,std_ln_1,std_ln_2,nlos,std_shdw] = uwb_sv_params( cm_num )
% Return S-V model parameters for standard UWB channel models
% Lam Cluster arrival rate (clusters per ns
www.eeworm.com/read/352343/10562390
m uwb_sv_params.m
function [Lam,lambda,Gam,gamma,std_ln_1,std_ln_2,nlos,std_shdw] = uwb_sv_params( cm_num )
% Return S-V model parameters for standard UWB channel models
% Lam Cluster arrival rate (clusters per ns
www.eeworm.com/read/423374/10564869
vhd tonetaba.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ToneTaba IS
PORT ( Index : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ;
CODE : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ;
HIGH : OU
www.eeworm.com/read/423374/10564872
vhd notetabs.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY NoteTabs IS
PORT ( clk : IN STD_LOGIC;
ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );
END;
AR
www.eeworm.com/read/423374/10564887
vhd top.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TOP IS -- 顶层设计
PORT ( CLK12MHZ1,HORL1 : IN STD_LOGIC;
INDEX1 : IN STD_LOGIC_VECTOR(
www.eeworm.com/read/423374/10564926
vhd mux21a.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mux21a IS
PORT( CLK12MHZ2,HORL2 : IN STD_LOGIC;
INDEX3 : IN STD_LOGIC_VECTOR(7 DOWNTO