代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/162264/10321588
vhd mult2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mult2 is
generic(a1:natural:=9;
b1:natural:=12;
q1:natural:=16);
port(clk:in std_logic;
res
www.eeworm.com/read/162264/10321591
vhd adjust1_mult.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.equ_pak.all;
entity adjust1_mult is
port(
clk:in std_logic;
resetn:in
www.eeworm.com/read/162264/10321594
vhd mult3.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mult3 is
generic(a1:natural;
b1:natural;
q1:natural);
port(clk:in std_logic;
resetn:in std_
www.eeworm.com/read/162264/10321605
vhd adjust3_mult.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.equ_pak.all; ------- 包体在所有的程序中要放在最前面----
www.eeworm.com/read/162264/10321633
vhd adjust2_mult.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.equ_pak.all;
entity adjust2_mult is
port(
clk:in std_logic;
resetn:in s
www.eeworm.com/read/354633/10340333
vhd finping8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenping8 is
port(clk_4m:in std_logic;
clk14,clk15:out std_logic);
end;
architecture art of fenp
www.eeworm.com/read/354633/10340400
vhd control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port(p0:in std_logic_vector(7 downto 0);
ale:in std_logic;
wr:in std_logic;
a:
www.eeworm.com/read/354548/10346256
vhd compressor_tb.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : JPEG Hardware Compressor Testbench
-- Design : jpeg
-- Author : Vi
www.eeworm.com/read/162008/10346919
txt 发送q_crc程序.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity crc is
port(clk,reset:in std_logic;
q1,q_crc:out std_logic;
q2:out std_logic_vector(15 downto 0))
www.eeworm.com/read/162008/10346930
txt 16串行总图程序.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity crc is
port(clk,reset:in std_logic;
q1,q_crc:out std_logic;
q2:out std_logic_vector(15 downto 0))