代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/360965/10070892
vhd fft.vhd
-- megafunction wizard: %FFT v7.1%
-- GENERATION: XML
-- ============================================================
-- Megafunction Name(s):
-- auk_dspip_r22sdf_top_fft_71
-- =============
www.eeworm.com/read/164962/10080335
txt counter_generate.txt
-- Generated Binary Up Counter
-- The first design entity is a T-type flip-flop.
-- The second is an scalable synchronous binary up counter illustrating the use of the generate statement to produce
www.eeworm.com/read/164942/10081140
vhd i60bcd.vhd
--The IEEE standard 1164 package, declares std_logic, rising_edge(), etc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity i60bcd i
www.eeworm.com/read/164942/10081157
vhd regne.vhd
--regne.vhd n-bit register with enable
library ieee ;
use ieee.std_logic_1164.all ;
entity regne is
generic ( n : integer := 12 ) ;
port (
r : in std_logic_vector(n-1 downto 0) ;--register
www.eeworm.com/read/164942/10081180
vhd negative.vhd
--negative.vhd correct negative number circuit
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity negative is
port(
a : in std_logic_vector(11 downto 0);--块
www.eeworm.com/read/164942/10081191
vhd bcdadd.vhd
--bcdadd.vhd 1 digit bcd adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcdadd is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/164942/10081195
vhd bcd.vhd
--bcd.vhd 1 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/164942/10081199
vhd multiplier.vhd
--multiplier.vhd n-bit multiplier
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity multiplier is
generic ( n : integer := 7; nn :
www.eeworm.com/read/164942/10081206
vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
www.eeworm.com/read/164302/10118753
vhd reg32b.vhd
library ieee;--锁存器
use ieee.std_logic_1164.all;
entity reg32b is
port(load: in std_logic;
din: in std_logic_vector(15 downto 0);
dout: out std_logic_vector(15 downto 0));
end e