代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
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vhd multiplier.vhd
--multiplier.vhd n-bit multiplier
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity multiplier is
generic ( n : integer := 7; nn :
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vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
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vhd reg16b.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity reg16b is
port(load: in std_logic;
din:in std_logic_vector(15 downto 0);
dout:out std_logic_vector(15 downto 0
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vhd reg8b.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity reg8b is
port(load: in std_logic;
din:in std_logic_vector(7 downto 0);
dout:out std_logic_vector(7 downto 0));
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vhd cnt10bcd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cnt10bcd is
Port ( clkin :in std_logic;
co :out std_logic;
qout
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vhd cpldnet.vhd
library ieee;
use ieee.std_logic_1164.all;
entity dwnldpar is
port(
-- parallel port data, control, and status pins
ppd: in std_logic_vector(7 downto 0);
ppc: in std_logic_vector(3 down
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vhd crcgenerator.vhd
-------------------------------------------------------------------------------
-- crcGenerator.vhd
--
-- Author(s): Jorgen Peddersen
-- Created: 19 Jan 2001
-- Last Modified: 26 Jan 20
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vhd control_fsm_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
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bak transceiver.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
Entity transceiver is
port (clk,rst_n,inEn1,inEn2,inEn3 :in std_logic;
SPI_SO,FIFO,FIFOP,SFD,CCA :in std_logic;
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vhd transceiver.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
Entity transceiver is
port (clk,rst_n,inEn1,inEn2,inEn3 :in std_logic;
SPI_SO,FIFO,FIFOP,SFD,CCA :in std_logic;