📄 transceiver.vhd.bak
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
Entity transceiver is
port (clk,rst_n,inEn1,inEn2,inEn3 :in std_logic;
SPI_SO,FIFO,FIFOP,SFD,CCA :in std_logic;
VREGEN,RESETn,SPI_SI,SPI_CSn:out std_logic;
trans_data,rec_data :out std_logic_vector(2 downto 0));
End transceiver;
Architecture rtl of transceiver is
component switch_cap is
port (clk,rst_n,switch:in std_logic;
switch_tring:out std_logic);
End component;
------------OutPut Reg--------------
signal trans_data_tmp:std_logic_vector(2 downto 0);
signal Vergen :std_logic;
signal Reset :std_logic;
signal SPI_SI_tmp :std_logic;
signal SPI_SCK_tmp :std_logic;
signal FIFO_tmp :std_logic;
signal tmp_FIFO :std_logic;
------------Middle Reg--------------
signal count :std_logic_vector(3 downto 0);
signal clk5m :std_logic;
signal clk2_5m :std_logic;
signal inEn1_tring :std_logic;
signal inEn2_tring :std_logic;
signal inEn3_tring :std_logic;
signal tring :std_logic;
------------Next Part Reg---------
signal state :std_logic_vector(9 downto 0);
signal counter0 :std_logic_vector(9 downto 0);
signal counter1 :std_logic_vector(2 downto 0);
signal counter2 :std_logic_vector(7 downto 0);
signal spi_value :std_logic_vector(23 downto 0);
signal State2_Step :std_logic_vector(3 downto 0);
signal trans_length :std_logic_vector(3 downto 0);
signal rec_length :std_logic_vector(3 downto 0);
signal oscillator :std_logic;
-----------Control Reg--------------
signal SPI_CS :std_logic;
signal counter :std_logic_vector(3 downto 0);
signal flag :std_logic;
-----------Trans and Reciev Reg------
signal addr_si :std_logic_vector(4 downto 0);
signal addr_so :std_logic_vector(2 downto 0);
signal current :std_logic_vector(7 downto 0);
signal num :std_logic_vector(7 downto 0);
signal tmp_data :std_logic_vector(11 downto 0);
signal flag1,flag2 :std_logic;
Begin ----Architectrue
process(clk,rst_n)
begin
if clk'event and clk='1'
then
if rst_n='0'
then
trans_data_tmp<="000";
else
trans_data_tmp(0)<=inEn1;
trans_data_tmp(0)<=inEn2;
trans_data_tmp(0)<=inEn3;
end if;
end if;
end process;
process(clk,rst_n)
begin
if clk'event and clk='1'
then
if rst_n='0'
then
count<="0000";
clk5m<='0';
clk2_5m<='0';
else
clk5m<=count(2);
clk2_5m<=count(3);
if count="1111"
then count<="0000";
else count<=count+"0001";
end if;
end if;
end if;
end process;
U1: switch_cap port map(clk2_5m,rst_n,inEn1,inEn1_tring);
U2: switch_cap port map(clk2_5m,rst_n,inEn2,inEn2_tring);
U3: switch_cap port map(clk2_5m,rst_n,inEn3,inEn3_tring);
tring<=inEn1_tring or inEn2_tring or inEn3_tring ;
--tmp_FIFO<= state!="0010000000" and state!="1000000000" or FIFO_tmp;
------ 10 State of the transciever---------
process(clk5m,rst_n)
Begin
if clk5m'event and clk5m='1'
then
if rst_n='0'
then
Vergen<='0';
state<="0000000001";
counter0<="0000000000";
counter1<="000";
ResetN<='1';
counter2<="00000000";
spi_value<="000000000000000000000000";
State2_Step<="000";
else
--------------- Begin 10 State---------------
case state is
when "0000000001" =>
Vergen<='1';
if counter0="1111111111"
then state<="0000000010";counter0<="0000000000";
else counter0<=counter0+"0000000001";
end if;
when "0000000010" =>
if Vergen='1'
then
if counter1="111"
then counter1<="000"; state<="0000000100";
else counter1<=counter1+"001";
end if;
if (counter1>"000") and (counter1<"101")
then ResetN <='0';
else ResetN <='1';
end if;
else
counter1<="000";
ResetN<='1';
state<="0000000001";
end if;
when "0000000100" =>
case State2_Step is
when "001" =>
spi_value<="000100010000001011000010";
if counter2="01110000"
then counter2<="00000000";State2_Step<="010";
else counter2<=counter2+"001";
end if;
when "010" =>
spi_value<="000100100000010100000101";
if counter2="01110000"
then counter2<="00000000";State2_Step<="100";
else counter2<=counter2+"001";
end if;
when "100" =>
spi_value<="000000010000000100000001";
if counter2="01110000"
then counter2<="00000000";State2_Step<="001";state<="0000001000";
else counter2<=counter2+"001";
end if;
when others=>State2_step<="001";
end case;
when "0000001000" =>
if oscillator='1'
then state<="0000010000";
else
spi_value<="000000010000000000000000";
if counter2="0111000"
then counter2<="00000000";state<="0000001000";
else counter2<=counter2+"001";
end if;
end if;
when "0000010000" =>
if tring='1'
then state<="0000100000";
else state<="0001000000";
end if;
when "0000100000" =>
spi_value<="000001000000010000000100";
if counter2="0111000"
then counter2<="00000000";state<="0010000000";
else counter2<=counter2+"001";
end if;
when "0001000000" =>
if tring='1'
then state<="0000100000";
else
spi_value<="000000110000001100000011";
if counter2="0111000"
then counter2<="00000000";state<="0100000000";
else counter2<=counter2+"001";
end if;
end if;
when "0010000000" =>
if trans_length="1011"
then state<="1000000000";
else state<="0010000000";
end if;
when "0100000000" =>
if tring='1'
then state<="0000100000";
else
if rec_length="1011"
then state<="1000000000";
else state<="0100000000";
end if;
end if;
when "1000000000" =>
if tring='1'
then state<="0000100000";
else
spi_value<="000001100000011000000110";
if counter2="0111000"
then counter2<="00000000";state<="0000010000";
else counter2<=counter2+"001";
end if;
end if;
when others => state<="0000000001";
end case;
end if;
End if;
end process;
process(clk5m,rst_n)
begin
if clk5m'event and clk5m='1'
then
if rst_n='0'
then SPI_CS<='0';
else
if (counter2>"00000000") and (counter2<"01101000")
then SPI_CS<='1';
else SPI_CS<='0';
end if;
end if;
SPI_CSn<= not SPI_CS;
end if;
end process;
process(clk5m,rst_n)
begin
if clk5m'event and clk5m='1'
then
if rst_n='1' and SPI_CS='1'
then
if counter="1111"
then
counter<="0000";flag<='0';
elsif flag='1'
then counter<=counter+"0001";
else flag<='1';
end if;
else counter<="0000";flag<='0';
end if;
SPI_SCK_tmp<=rst_n and counter(0);
SPI_SCK<=SPI_SCK_tmp;
end if;
end process;
process(SPI_SCK_tmp,rst_n)
begin
if SPI_SCK_tmp'event and SPI_SCK_tmp='0'
then
if rst_n='0'
then
SPI_SI_tmp<=spi_value(23);
addr_si<="10110"; ------// 22
else
if SPI_CS='1'
then
SPI_SI_tmp<=spi_value(addr_si);
if addr_si="00000"
then addr_si<="10111";
else addr_si<=addr_si-"00001";
end if;
else
SPI_SI_tmp<=spi_value(23);
addr_si<="10110";
end if;
end if;
end if;
end process;
process(SPI_SCK_tmp,rst_n)
begin
if SPI_SCK_tmp'event and SPI_SCK_tmp='1'
then
if rst_n='0'
then
addr_so<="111";
current<="00000000";
oscillator<='0';
else
if SPI_CS='1'
then
if addr_so="000"
then addr_so<="111";
else addr_so<=addr_so-"001";
end if;
current(addr_so)<=SPI_SO;
oscillator<=current(6);
else
addr_so<="111";
current<="00000000";
end if;
end if;
end if;
end process;
process(FIFOP,rst_n)
begin
if FIFOP'event and FIFOP='0'
then
if rst_n='0'
then
FIFO_tmp<='1';
trans_length<="0000";
num<="00000001";
else
if state="0010000000"
then
if trans_length<"1011"
then
if num<"1000"
then FIFO_tmp<='1';num<=num+"00000001";
else
if trans_length<"0011"
then FIFO_tmp<=trans_data(trans_length);trans_length<=trans_length+"0001";
else FIFO_tmp<='0';trans_length<=trans_length+"0001";
end if;
end if;
else trans_length<="0000";num<="0001";
end if;
else FIFO_tmp<='1';trans_length<="0000";num<="0001";
end if;
end if;
end if;
end process;
process(clk5m,rst_n,FIFOP)
begin
if clk5m'event and clk5m='1'
then
if rst_n='0'
then flag1<='0';flag2<='0';
else flag1<=FIFOP;flag2<=flag1;
end if;
end if;
end process;
process(clk5m,rst_n)
begin
if clk5m'event and clk5m='1'
then
if rst_n='0'
then tmp_data<="00000000000";rec_length<="0000";
else
if state="0100000000"
then
if SFD='1'
then
if flag1='1' and flag2='0'
then
if rec_length<"1011"
then tmp_data(rec_length)<=tmp_FIFO;rec_length<=rec_length+1;
end if;
end if;
else rec_length<="0000";
end if;
else rec_length<="0000";
end if;
end if;
end if;
end process;
process(clk5m,rst_n)
begin
if clk5m'event and clk5m='1'
then
if rst_n='0'
then rec_data<="000";
elsif tmp_data(7 downto 0)="11111111"
then rec_data<=tmp_data(10 downto 8);
end if;
end if;
end process;
end rtl;
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