代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/378278/9238623
vhd arith_lib.vhd
-------------------------------------------------------------------------------
-- Title : Library component declarations
-- Project : VHDL Library of Arithmetic Units
----------------------
www.eeworm.com/read/378191/9242124
vhd ane.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ane is
port (cho: in std_logic;
ane: out std_logic);
end entity ane;
architecture one of ane is
signal
www.eeworm.com/read/181565/9245797
m uwb_sv_params.m
function [Lam,lambda,Gam,gamma,std_ln_1,std_ln_2,nlos,std_shdw] = uwb_sv_params( cm_num )
% Return S-V model parameters for standard UWB channel models
% Lam Cluster arrival rate (clusters per ns
www.eeworm.com/read/181432/9255488
vhd system.vhd
-- ------------------------------------------------
-- Model : Top - Level System Component
--
-- Author : Michael Mayer,
-- Department of Electrical Engineering
-- Uni
www.eeworm.com/read/377612/9269624
th ramtestbench.th
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dualram_tb is
end entity;
architecture Behavioral of dualram_tb is
constant
www.eeworm.com/read/377553/9271604
vhd i60bcd.vhd
--The IEEE standard 1164 package, declares std_logic, rising_edge(), etc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity i60bcd i
www.eeworm.com/read/377553/9271613
vhd regne.vhd
--regne.vhd n-bit register with enable
library ieee ;
use ieee.std_logic_1164.all ;
entity regne is
generic ( n : integer := 12 ) ;
port (
r : in std_logic_vector(n-1 downto 0) ;--register
www.eeworm.com/read/377553/9271632
vhd negative.vhd
--negative.vhd correct negative number circuit
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity negative is
port(
a : in std_logic_vector(11 downto 0);--块
www.eeworm.com/read/377553/9271641
vhd bcdadd.vhd
--bcdadd.vhd 1 digit bcd adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcdadd is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/377553/9271644
vhd bcd.vhd
--bcd.vhd 1 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd is
port(
a : in std_logic_vector(3 downto 0);--砆