ane.vhd

VHDL多功能时钟设计~~24小时制~带闹钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ane is
port (cho: in std_logic;
      ane: out std_logic);
end entity ane;
architecture one of ane is
signal a: integer range 0 to 1;
begin
  process(cho,a)
   begin
    if rising_edge(cho) then
     case a is
      when 0=>
      a<=1;
      ane<='0';
      when 1=>
      a<=0;
      ane<='1';
      when others=>null;
     end case;
   end if;
 end process;
end one;